ST16C654CJ68 EXAR [Exar Corporation], ST16C654CJ68 Datasheet - Page 23

• Manufacturer Part Number: ST16C654CJ68
• Description: QUAD UART WITH 64-BYTE FIFO AND INFRARED (IrDA) ENCODER/DECODER
• Manufacturer: EXAR [Exar Corporation]

REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the fifteen 654 internal registers. The assigned
bit functions are more fully defined in the following paragraphs.
Rev. 4.10
A2 A1 A0
0
0
0
0
0
0
1
1
1
1
0
0
General Register Set
Special Register set: Note *2
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
Register
[Default]
RHR[XX]
THR[XX]
MCR[00]
MSR[X0]
DLM[XX]
SPR[FF]
LCR[00]
DLL[XX]
LSR[60]
Note *5
IER[00]
ISR[01]
FCR
Table 6, ST16C654 INTERNAL REGISTERS
interrupt
enabled
FIFO’s
divisor
RCVR
trigger
(MSB)
enable
select
BIT-7
Clock
FIFO
bit-15
CTS
latch
error
bit-7
bit-7
bit-7
data
bit-7
CD
interrupt
enabled
FIFO’s
RCVR
trigger
enable
BIT-6
(LSB)
trans.
empty
break
bit-14
RTS
bit-6
bit-6
bit-6
bit-6
set
IR
RI
interrupt
holding
(MSB)
priority
trigger
empty
BIT-5
trans.
bit-13
parity
DSR
bit-5
bit-5
bit-4
bit-5
Xoff
bit-5
INT
Xon
Any
set
TX
5-87
interrupt
priority
trigger
(LSB)
BIT-4
Sleep
bit-12
mode
parity
break
even
back
CTS
bit-4
bit-4
bit-4
bit-3
loop
bit-4
INT
TX
ST16C654/654D
interrupt
modem
framing
enable
priority
enable
status
select
-OP2/
BIT-3
mode
parity
bit-11
DMA
INTx
error
delta
bit-3
bit-3
bit-2
bit-3
bit-3
-CD
INT
interrupt
receive
priority
status
BIT-2
XMIT
bit-10
FIFO
-OP1
parity
reset
error
delta
bit-2
bit-2
bit-1
bit-2
bit-2
stop
INT
line
bits
-RI
transmit
register
overrun
holding
RCVR
priority
length
BIT-1
-DSR
FIFO
-RTS
reset
bit-1
word
error
delta
bit-1
bit-0
bit-1
bit-1
bit-1
bit-9
INT
register
receive
holding
receive
enable
length
BIT-0
status
-DTR
ready
-CTS
FIFO
word
delta
bit-0
bit-0
bit-0
data
bit-0
bit-0
bit-8
INT