ST16C2552CJ44 EXAR [Exar Corporation], ST16C2552CJ44 Datasheet - Page 14

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ST16C2552CJ44

Manufacturer Part Number
ST16C2552CJ44
Description
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
Manufacturer
EXAR [Exar Corporation]
Datasheet

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ST16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
The 2552 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 11
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
2.12
Internal Loopback
shows how the modem port signals are re-configured. Transmit data from the transmit shift register
F
IGURE
11. I
NTERNAL
Transmit Shift Register
Receive Shift Register
L
OOP
(RHR/FIFO)
(THR/FIFO)
B
ACK IN
C
DTR#
DSR#
RTS#
CTS#
OP2#
RI#
CD#
HANNEL
MCR bit-4=1
14
VCC
VCC
A
OP1#
VCC
VCC
AND
B
TXA/TXB
RXA/RXB
RTSA#/RTSB#
CTSA#/CTSB
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
(OP2A#/OP2B#)
REV. 4.2.1

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