ST16C2550CQ48 EXAR [Exar Corporation], ST16C2550CQ48 Datasheet - Page 7

• Manufacturer Part Number: ST16C2550CQ48
• Description: 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

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ST16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 4.4.0
1.0 PRODUCT DESCRIPTION
The ST16C2550 (C2550) integrates the functions of two 16C550 Universal Asynchrounous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The C2550 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-
to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for
converting the serial data stream into parallel data that is required with digital data systems. Synchronization
for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to
provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip.
The C2550 represents such an integration with greatly enhanced features. The C2550 is fabricated with an
advanced CMOS process.
The C2550 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive
FIFO memory, instead of none in the 16C2450. The C2550 is designed to work with high speed modems and
shared network environments, that require fast data processing time. Increased performance is realized in the
C2550 by the transmit and receive FIFO’s. This allows the external processor to handle more networking tasks
within a given time. For example, the ST16C2450 without a receive FIFO, will require unloading of the RHR in
93 microseconds (This example uses a character length of 11 bits, including start/stop bits at 115.2 Kbps). This
means the external CPU will have to service the receive FIFO less than every 100 microseconds. However
with the 16 byte FIFO in the C2550, the data buffer will not require unloading/loading for 1.53 ms. This
increases the service interval giving the external CPU additional time for other applications and reducing the
overall UART interrupt servicing time. In addition, the 4 selectable receive FIFO trigger interrupt levels is
uniquely provided for maximum data throughput performance especially when operating in a multi-channel
environment. The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU,
increases performance, and reduces power consumption.
The C2550 is capable of operation up to 4 Mbps with a 64 MHz external clock. With a crystal or external clock
input of 14.7456 MHz the user can select data rates up to 921.6 Kbps.
The rich feature set of the C2550 is available through internal registers. Selectable receive FIFO trigger levels,
selectable TX and RX baud rates, and modem interface controls are all standard features. Following a power
on reset or an external reset, the C2550 is software compatible with the previous generation, ST16C2450.
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