ST16C2550CQ48 EXAR [Exar Corporation], ST16C2550CQ48 Datasheet - Page 6

• Manufacturer Part Number: ST16C2550CQ48
• Description: 2.97V TO 5.5V DUART WITH 16-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

ST16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
Pin Description
N
ANCILLARY SIGNALS
OTE
DSRB#
RESET
CTSB#
DTRB#
OP2B#
XTAL1
XTAL2
CDB#
N
RIB#
GND
VCC
N.C.
: Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
AME
40-PDIP
P
25
34
22
19
23
13
16
17
35
40
20
IN
-
#
44-PLCC
P
28
38
25
21
26
15
18
19
39
44
22
IN
-
#
12, 24, 25,
48-TQFP
P
23
35
20
16
21
13
14
36
42
17
37
IN
9
#
T
Pwr
Pwr
YPE
O
O
O
I
I
I
I
I
I
6
UART channel B Clear-to-Send (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
UART channel B Data-Terminal-Ready (active low) or
general purpose output. If it is not used, leave it uncon-
nected.
UART channel B Data-Set-Ready (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
UART channel B Carrier-Detect (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
UART channel B Ring-Indicator (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
Output Port 2 Channel B - The output state is defined by
the user and through the software setting of MCR[3].
INTB is set to the active mode and OP2B# output to a
logic 0 when MCR[3] is set to a logic 1. INTB is set to the
three state mode and OP2B# to a logic 1 when MCR[3] is
set to a logic 0. See MCR[3]. This output should not be
used as a general output else it will disturb the INTB out-
put functionality. If it is not used, leave it unconnected.
Crystal or external clock input.
Crystal or buffered clock output.
Reset (active high) - A longer than 40 ns logic 1 pulse on
this pin will reset the internal registers and all outputs.
The UART transmitter output will be held at logic 1, the
receiver input will be ignored and outputs are reset during
reset period (see External Reset Conditions).
2.97V to 5.5V power supply. All inputs are 5V tolerant for
devices with top marking of "A2 YYWW" and newer.
Power supply common, ground.
No Connection. These pins are open, but typically, should
be connected to GND for good design practice.
D
ESCRIPTION
xr
REV. 4.4.0