ST72521 STMICROELECTRONICS [STMicroelectronics], ST72521 Datasheet - Page 130

• Manufacturer Part Number: ST72521
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72521
CONTROLLER AREA NETWORK (Cont’d)
10.8.3.3 Modes of Operation
The CAN Core unit assumes one of the seven
states described below:
– STANDBY. Standby mode is entered either on a
Figure 69. CAN Controller State Diagram
n
130/211
chip reset or on resetting the RUN bit in the Con-
trol/Status Register (CSR). Any on-going trans-
mission or reception operation is not interrupted
and completes normally before the Bit Time Log-
ic and the clock prescaler are turned off for mini-
mum power consumption. This state is signalled
by the RUN bit being read-back as 0.
Once in standby, the only event monitored is the
reception of a dominant bit which causes a wake-
up interrupt if the SCIE bit of the Interrupt Control
Write to DATA7 |
TX Error & NRTX
TRANSMISSION
TX Error
RUN
RUN
TX OK
Arbitration lost
STANDBY
RESYNC
ARESET
ERROR
IDLE
FSYN & BOFF & 11 Recessive bits |
(FSYN | BOFF) & 128 * 11 Recessive bits
RX OK
– WAKE-UP. The CAN bus line is forced to domi-
RUN & WKPS
Register (ICR) is set.
The STANDBY mode is left by setting the RUN
bit. If the WKPS bit is set in the CSR register,
then the controller passes through WAKE-UP
otherwise it enters RESYNC directly.
It is important to note that the wake-up mecha-
nism is software-driven and therefore carries a
significant time overhead. All messages received
after the wake-up bit and before the controller is
set to run and has completed synchronization
are ignored.
nant for one bit time signalling the wake-up con-
dition to all other bus members.
BOFF
RUN & WKPS
BOFF
RECEPTION
Start Of Frame
RX Error
WAKE-UP