ml6652 Sirenza Microdevices, ml6652 Datasheet - Page 10

• Manufacturer Part Number: ml6652
• Description: 10/100mbps Ethernet Fiber And Copper Media Converter With Auto-negotiation
• Manufacturer: Sirenza Microdevices

10
Pin No. Signal Name
PIN DESCRIPTIONS (continued)
36
33
32
30
29
FOINN
FOINP
CQOS
SDFO
RTOP
I / O
O
I
I
I
January 2004
Description
implemented, a 1kΩ off-chip resistor should be connected to ground and a 1nF
capacitor connected to IOUT. These components determine the peaking
current waveform. When peaking is not used, IOUT# should connect to VCC
PECL/LVPECL Compatible Interface Mode:
PECL/LVPECL interface positive and complementary outputs. These outputs
form a differential current output pair that drives NRZI encoded 100BASE-SX or
100BASE-FX symbols during 100Mbps mode, Manchester encoded 10BASE-
FL data or OPT_IDL during 10Mbps mode, and FLNP Bursts during Auto-
Negotiation. IOUT and IOUT# are loaded with external resistors to VCC and
AC coupled to the inputs of a fiber optic PMD module (refer to description of
RTOP pin). A resistor network may be needed to setup the common mode
voltage at the input pins of the PMD module
Fiber optic LED or PECL/LVPECL driver bias resistor. An external resistor
connected between RTOP and ground sets a constant bias current for the single
ended LED driver or differential PECL/LVPECL driver circuitry. These output
currents depend on the operating mode.
The recommended external component values are:
Fiber Optic Interface mode: (1% resistors, +/- 10% currents)
Indicated is the current into pin IOUT during the High-Light state.
2.8kΩ between RTOP and ground for 50mA.
2kΩ between RTOP and ground for 70mA.
1.4kΩ between RTOP and ground for 100mA.
PECL/LVPECL Interface mode:
1.4kΩ, 1%, between RTOP and ground for 10mA current.
Equivalent 62Ω between IOUT and VCC.
Equivalent 62Ω between IOUT# and VCC.
Also AC coupled to PMD inputs
The two operating modes available for these pins and are selected with the
configuration pin PECLQU or the configuration bit PECLQU <30.7>
Fiber Optic Interface Mode:
Fiber optic quantizer positive and complementary inputs. FOINP is
capacitively coupled to the output of a fiber optic receiver, while FOINN is
capacitively coupled to the VCC of the fiber optic receiver. Recommended
capacitor values: 10nF, 5%. FOINP voltage must be higher during the “high
light” state than during the low-light state
PECL/LVPECL Compatible Interface Mode:
PECL/LVPECL interface positive and complementary inputs. These inputs form
a differential input pair that receives 100BASE-FX, 100BASE-SX, FLNP Bursts,
or 10BASE-FL signal from a fiber optic PMD. The PMD outputs are AC coupled
to these inputs with 10nF, 5% capacitors. The common mode voltage is set
internally with ~900Ω (or so) resistors from each input pin to an on-chip
voltage reference. FOINP voltage must be higher during the “high light” state
than during the "low light" state
Data quantizer offset cancellation loop capacitor. An external capacitor
between this pin and VCC determines the dominant pole of the offset
cancellation feedback loop. The recommended value is .1µF, 10%. It is only
required in "Fiber Optic Interface" mode.
The two operating modes available for this pin are selected with the
configuration pin PECLQU or the configuration bit PECLQU <30.7>
Fiber Optic Interface Mode:
This pin is not used and should be connected to VCC.
Final Datasheet
DS6652-F-02
ML6652