ST16 STMICROELECTRONICS [STMicroelectronics], ST16 Datasheet - Page 10

• Manufacturer Part Number: ST16
• Description: CHIP SET INTERFACE SPECIFICATION
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST16-19RFRDCS
Figure 3 FPGA read access chronogram for last byte
Before sending the last byte the FPGA takes the Rx_fifo_empty line high to indicate to the MCU that this
is the last data.
1.3.5 MCU interface timings
The following board provides interface timings (cf previous chronogram)
Table 1 : Interface timing
4/15
Timing
t0
t1
t2
t3
t4
t5
t6
Rx_irq_eof to Mic_Strb_b Transition
Mic_Ctrl_Data, Mic_RW (and Mic_Data in writing) Setup Time before
Mic_Strb_b Low Transition
Mic_Ctrl_Data, Mic_RW (and Mic_Data in writing) Hold Time before
Mic_Strb_b High Transition
Mic_Strb_b Width Low (Activ)
Mic_Strb_b Width High (Inactiv)
Mic_Strb_b Activ to Valid Data in Reading
Mic_Strb_b Inactiv to Tri-States Data in Reading
Mic_Ctrl_Data
Mic_Data(7:0)
Rx_fifo_empty
Rx_irq_eof
Mic_RW
Mic_Strb_b
Tx_start
Tx_fifo_empty
t0
Parameter
t1
Acquisition of the last byte
t3
t5
t6
t2
t4
FSD_CHIPSET_B/0104VP2
Min. (ns)
240
80
0
0
0
Max. (ns)
240
20