lxt362 Intel Corporation, lxt362 Datasheet - Page 32

• Manufacturer Part Number: lxt362
• Description: Integrated T1 Lh/sh Transceiver For Ds1/dsx-1 Or Pri Applications
• Manufacturer: Intel Corporation

LXT362 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
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1. Leaving a 1 of in any of these bits masks the associated interrupt.
1. A QRSS transition indicates receive QRSS pattern sync or loss. A simple error in QRSS pattern is not reported as a
2. Tripping the overflow or underflow indicator in the ES sets the ESOVR/ESUNF status bit(s). Reading the Transition Status
Bit
Bit
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
transition.
Register clears these bits. Setting CESO and CESU in the Interrupt Clear Register masks these interrupts.
Table 13. Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x
Table 14. Transition Status Register Read Only, Address (A7-A0) = x010100x
CNLOOP
CDFMO
CQRSS
Name
CLOS
CESO
CESU
CAIS
TNLOOP
TDFMO
TQRSS
ESOVR
ESUNF
Name
TLOS
-
TAIS
-
1 = Clear/Mask Loss of Signal interrupt.
0 = Enable Loss of Signal interrupt.
1 = Clear/Mask Network loopback interrupt.
0 = Enable Network loopback interrupt.
1 = Clear/Mask Alarm Indication Signal interrupt.
0 = Enable Alarm Indication Signal interrupt.
1 = Clear/Mask Quasi-Random Signal Source interrupt.
0 = Enable Quasi-Random Signal Source interrupt.
Reserved. Set to 1 for normal operation.
1 = Clear/Mask Driver Failure Monitor Open interrupt.
0 = Enable Driver Failure Monitor Open interrupt.
1 = Clear/Mask Elastic Store Overflow interrupt.
0 = Enable Elastic Store Overflow interrupt.
1 = Clear/Mask Elastic Store Underflow interrupt.
0 = Enable Elastic Store Underflow interrupt.
1 = Loss of Signal (LOS) has changed since last clear LOS interrupt occurred.
0 = No change in status.
1 = NLOOP has changed since last clear NLOOP interrupt occurred.
0 = No change in status.
1 = AIS has changed since last clear AIS interrupt occurred.
0 = No change in status.
1 = QRSS has changed since last clear QRSS interrupt occurred
0 = No change in status.
Reserved. Ignore.
1 = DFMO has changed since last clear DFMS interrupt occurred.
0 = No change in status.
1 = ES overflow status sticky bit
0 = No change in status.
1 = ES underflow status sticky bit
0 = No change in status.
2
.
2
.
Function
Function
1
1
.
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