SM5844 NPC [Nippon Precision Circuits Inc], SM5844 Datasheet - Page 18

• Manufacturer Part Number: SM5844
• Description: Asynchronous Sample Rate Converter
• Manufacturer: NPC [Nippon Precision Circuits Inc]

System Clock
Input system clock (ICLK, ICKSL)
The input system clock can be set to run at either
256fsi or 384fsi, where fsi is the input frequency on
LRCI.
Note that ICLK and LRCI should be divided from a
common clock source or PLL to maintain
synchronism.
Table 9. ICLK system clock
Output data interface and output clock selection (LRCO, BCKO, DOUT, SLAVE)
Table 11. Output mode description
1. The number of BCKO input clock cycles should not exceed 64 per word. Correct operation is not guaranteed beyond these limits.
System Reset (RSTN)
At power-ON, all device functions must be reset. The
device is reset by applying a LOW-level pulse on
RSTN. At system reset, the internal arithmetic
operation, output timing counter and internal flag
register operation are synchronized on the next LRCI
rising edge. Note that all flags are set to their defaults
(all LOW).
A power-ON reset signal can be applied from an
external microcontroller. For systems where ICLK
and LRCI are stable at power ON, initialization can
be performed by connecting a 0.001 µF capacitor
between RSTN and VSS. Otherwise, a capacitor
value should be chosen such that RSTN does not go
HIGH until after LRCI and ICLK have stabilized.
T H R U N
H I G H
L O W
I C K S L
H I G H
L O W
S L AV E
H I G H
L O W
Master mode
Slave mode
Through mode
ICLK system clock rate
M o d e
384fsi
256fsi
Output word clock (LRCO) and output bit clock
( B C KO) are divided from OCLK.
Output word clock (LRCO) and output bit clock
( B C KO) are supplied externally.
Output word clock (LRCO), output bit clock
( B C KO) and output data (DOUT) are the
same as LRCI, BCKI and DI, respectively.
SM5844AF
Output system clock (OCLK, OCKSL)
The output system clock can be set to run at either
256fso or 384fso, where fso is the input frequency on
LRCO. In through mode, OCLK and OCKSL have
no function and are not used.
Note that in slave mode, a suitable clock must be
input on OCLK. The clock on OCLK should ideally
have a protection circuit to prevent incorrect
operation for times when the clock on ICLK is
halted.
Table 10. OCLK system clock
Through Mode (THRUN)
Table 12. THRUN operation
T H R U N
S L AV E
H I G H
H I G H
L O W
L O W
Description
Function
Through mode
Nor mal mode
O C K S L
H I G H
L O W
M o d e
NIPPON PRECISION CIRCUITS—18
Direct connections are made: LRCI
to LRCO, BCKI to BCKO , and DI to
D O U T.
Sample rate converter operation
O C L K s y s t e m clock rate
L R C O , B C KO state
Not used
384fso
256fso
Description
Outputs
Outputs
Inputs
1