SM5844 NPC [Nippon Precision Circuits Inc], SM5844 Datasheet - Page 13

• Manufacturer Part Number: SM5844
• Description: Asynchronous Sample Rate Converter
• Manufacturer: NPC [Nippon Precision Circuits Inc]

Microcontroller Interface (MCOM, MDT, MCK, MLEN)
When MCOM is HIGH, MDT (data), MCK (clock)
and MLEN (latch enable clock) interface pins are
used.
Input data on MDT is synchronized to the MCK
clock. Data is read into the input stage shift register
on the rising edge of MCK. Accordingly, the input
data should change on the falling edge of MCK.
Input data enters an internal SIPO (serial-to-parallel
converter register), and then the parallel data is
MLEN
MLEN
MDT
MCK
MCK
MDT
HIGH
B1
LOW
B1
B2
Figure 1. Attenuation data format (B1 = LOW)
Figure 2. Mode flag data format (B1 = HIGH)
Not used
* *
MSB
B2
a0
B5
B3
a1
FTST1
B6
SM5844AF
B4
a2
FTST2
B7
latched into the mode register on the rising edge of
the latch enable clock MLEN.
The mode register addressed is determined by the 1st
bit of the 12 data bits before MLEN goes HIGH. If
this bit is LOW, then the data is read into the
attenuation data register as shown in figure 1. If this
bit is HIGH, then the data is read into the mode flag
register as shown in figure 2. The function of each bit
in the mode flag register is described in table 1.
FRATE
B8
B8
a6
F12DB
B9
B9
a7
FFSI1
B10
NIPPON PRECISION CIRCUITS—13
MCK and MLEN can also follow the dotted lines.
MCK and MLEN can also follow the dotted lines.
B10
a8
FFSI2
B11
B11
a9
FDEEM
B12
LSB
B12
a10