gc41c501g2-so24i CORERIVER Semiconductor, gc41c501g2-so24i Datasheet - Page 14
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gc41c501g2-so24i
Manufacturer Part Number
gc41c501g2-so24i
Description
4-bit Microcontrollers With Reduced 8051 Architecture
Manufacturer
CORERIVER Semiconductor
Datasheet
1.GC41C501G2-SO24I.pdf
(55 pages)
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6.4. CPU Timing
CPU takes 6 clocks for a machine cycle.
Any instruction except branch instructions completes in one machine cycle.
All branch instruction consumes 2 machine cycles whether the branch is taken or not.
The state of SFR, I/O ports, or IFF flags changes at the end of an instruction (S6).
Program Counter
System Clock
Instruction
Register
CPU State
S1
S2
Execution Cycle N-1
Machine Cycle
Op. Code (N-1)
Fetch Cycle N
S3
N
S4
S5
S6
S1
S2
Execution Cycle N
Op. Code (N)
Fetch Cycle N+1
Machine Cycle
S3
N+1
ATOM1.2 Family
S4
S5
Preliminary
S6
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