hy5du281622ftp Hynix Semiconductor, hy5du281622ftp Datasheet - Page 3

• Manufacturer Part Number: hy5du281622ftp
• Description: 128mb Ddr Sdram
• Manufacturer: Hynix Semiconductor

Rev. 1.0 /June 2008
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ORDERING INFORMATION
* X means speed grade
** Lead-free product
*ROHS (Restriction Of Hazardous Substances)
DESCRIPTION
The HY5DU281622FT(P) is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the
main memory applications which requires large memory density and high bandwidth.
This Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
HY5DU281622F(L)TP-X*
V
(Typical 2.5V Operation +/- 0.2V for DDR266, 333)
V
(Typical 2.6V Operation +0.1/- 0.2V for DDR400,
400Mbps/pin product and 500Mbps/pin product )
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
DD
DD
Part No.
, V
, V
DDQ
DDQ
= 2.3V min ~ 2.7V max
= 2.4V min ~ 2.7V max
Configuration Package
8Mx16
TSOP-II**
400mil
66pin
OPERATING FREQUENCY
Grade
-D43
-D4
- K
- H
- J
-4
-5
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All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
Programmable CAS latency 2/2.5 (DDR266, 333)
and 3/4 (DDR400, 400Mbps/pin product and
500Mbps/pin product) supported
Programmable burst length 2/4/8 with both sequen-
tial and interleave mode
Internal four bank operations with single pulsed
/RAS
Auto refresh and self refresh supported
t
4096 refresh cycles/64ms
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Lead free (*ROHS Compliant)
RAS
133MHz@CL2
133MHz@CL2
100MHz@CL2
200MHz@CL3 / 100MHz @CL2
200MHz@CL3 / 100MHz @CL2
200MHz@CL3 / 100MHz @CL2
lock out function supported
Clock Rate
250MHz@CL4
HY5DU281622FT(P) Series
166MHz @CL2.5
133MHz@CL2.5
133MHz@CL2.5
& @CL3
500Mbps/pin (maxi-
400Mbps/pin (maxi-
DDR266B (2.5-3-3)
DDR333 (2.5-3-3)
DDR400B (3-3-3)
DDR266A (2-3-3)
DDR333 (3-3-3)
mum Date rate)
mum Date rate)
DDR400 (3-4-4)
Remark
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