m65818afp Renesas Electronics Corporation., m65818afp Datasheet - Page 16

• Manufacturer Part Number: m65818afp
• Description: Digital Amplifier Processor Of S-master* Technology
• Manufacturer: Renesas Electronics Corporation.

M65818AFP
M65818AFP detects rise edge of these synchronized clock in normal operation, and the M65818AFP does operation of
resynchronization in case that the cycle has changed.
In addition, the M65818AFP re-synchronizes for a synchronized clock, in case that M65818AFP detects SYNC pin's
rises edge, too.
This SYNC function exists also in serial control "System2 mode:bit6" under the same name.
While re-synchronizing, SFLAG pin outputs "H" and data is muted inside.
Input Signal Mode
Normal
External 8fs Data
SACD-fsi
SACD-fso
* Internal 8 dividing clock
In the case of using Multiplex(for multi channel application) and Single (for 2ch application) , detail explanation is
shown according to each "signal input mode" below.
• Normal Mode
<Multiplex use>
<Single use>
In this mode, M65818AFP always perform synchronous detection between LRCK pin's clock in primary side.
Therefore with regardless to a setup by the serial control "System1 mode:bit16(ASYNCEN1)", the synchronous
detection perform as ` forced-enable`.
• External 8fs Data Mode (The case of primary side synchronization)
<Multiplex use>
Rev.1.00, Sep.04.2003, page 16 of 38
The primary side: It synchronizes with LRCK. All ICs synchronize with an input device by connecting common
LRCK.
The Secondary side: It synchronizes with FsoCKO of Master IC. One of M65818AFP becomes a master IC, and the
synchronization between ICs is carried out by FsoCKO of Master IC.
FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs.
The primary side: It synchronizes with LRCK. Therefore M65818AFP synchronizes with source devices.
The secondary side: there is no need for external devices and other ICs to synchronize, therefore FsoCKO is
connected to FsoI, In other way, By setting secondary side asynchronous detection to "disable" with "ASYNCEN2"
flag(Serial Control,System2 mode,bit8), FsoI can also be considered as fixation.
The primary side: M65818AFP synchronizes with EXWCK (internal 8 dividing clock). All ICs synchronize with
an input device by connecting common EXWCK.
The secondary side: M65818AFP synchronizes with FsoCKO of Master IC. One of M65818AFP becomes a master
IC, and the synchronization between ICs is carried out by FsoCKO of Master IC.
FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs.
Primary Side Synchronization
Secondary Side Synchronization
`Synchronization detection` clock
Primary Side
LRCK
EXWCK *
FsiI
Secondary Side
FsoI
FsoI
FsoI
FsoI
FsoI