m65818afp Renesas Electronics Corporation., m65818afp Datasheet - Page 13

• Manufacturer Part Number: m65818afp
• Description: Digital Amplifier Processor Of S-master* Technology
• Manufacturer: Renesas Electronics Corporation.

M65818AFP
In case an external 8fs data input is primary side synchronous , the data is inputted to Sampling Rate Converter Block.
When "input signal mode" is except a "external 8fs data mode", the output data of sampling rate converter are outputted
from EXDATAL,EXDATAR pins setting up EXIOSEL pin into "H".
When "input signal mode" is except a "external 8fs data mode", EXBCK, EXWCK, EXDATAL, EXDATAR pins
serve as input terminals by setting up EXIOSEL pin into "L" .
Therefore, when not using "external 8fs data mode", EXIOSEL can be set to "L" and other four pins (EXBCK,
EXWCK, EXDATAL, EXDATAR) can be fixed to "L" or "H".
EXDATAL,EXDATAR,EXBCK, and EXWCK pin's input/output format is following figure.
Input Signal Mode
"External 8fs Mode"
(MODE1,2=L,H)
Except "External 8fs
Mode"
(Except MODE1,2=L,H)
•
5.5. DSDL, DSDR, DSD128Fs, DSD64Fs, DSDCKSEL1, DSDCKSEL2, DSDCKIO 50 49 47 48 51 52 53
When "input signal mode" is "SACD-fsi Mode" or "SACD-fso Mode", the data is inputted to DSDL,DSDR pins.
Under `SACD-fsi ` mode, the clock of a Down Sampling Filter is given from a primary side, and down sampled data
are inputted into the Sampling Rate Converter block.
Under `SACD-fso ` mode, the clock of a Down Sampling Filter is given from a *secondary side, and down sampled
data a inputted into the Gain Control block.
The states of DSDCKSEL1,DSDCKDEL2 pins select 4 "SACD timing mode".
DSDCKIO pin select input or output pin-type of DSD128Fs/DSD64Fs clock for data fetch.
The relations of DSDCKSEL1 and DSDCKSEL2 pins and SACD input format mode setting are following figures.
DSDCKSEL1
L
L
H
H
Rev.1.00, Sep.04.2003, page 13 of 38
EXDATAL, EXDATAR, EXBCK, and EXWCK input/output format
EXDATAL
/EXDATAR
EXWCK
EXBCK
256fs
EXIOSEL
pin
X
L
H
8fs
MSB
23
DSDCKSEL2
L
H
L
H
22
21
EXMODE
Flag
L
H
X
20
MSB first left justified (24bit)
EXWCK,EXBCK,EXDATAL,EXDATAR
Input / Output
Secondary Side Synchronous 8fs Data Input
(24 bit effective)
Primary Side Synchronous 8fs Data Input
(Upper 20bit effective)
Input ("L" or "H" fixed)
Internal Sampling Rate Converter Output
9
8
7
SACD timing mode
mode1
mode2
mode3
mode4
1
LSB
0