m66006 Mitsumi Electronics, Corp., m66006 Datasheet - Page 2

• Manufacturer Part Number: m66006
• Description: 12-bit I/o Expander
• Manufacturer: Mitsumi Electronics, Corp.

FUNCTION
The M66006 realizes low power dissipation and high noise
immunity by applying silicon CMOS process.
Because a 12-bit serial-parallel shift register and a 12-bit par-
allel-serial shift register are independently built in this IC, it is
possible to read serial input data while converting parallel
data into serial data.
When CS changes from “H” to “L”, serial output of 12-bit par-
allel data and read of serial data from the MCU start. That is,
12-bit parallel data is latched at the falling edge of CS, syn-
chronized with the falling edge of shift clock, and then output
to serial output pin DO as serial data. At the same time, serial
data from the MCU is read to the internal shift register at the
rising edge of shift clock. The shift clock on and after 13th bit
is neglected and pin DO is put in the high impedance state
when the reading operation is masked. When CS changes
from “L” to “H”, 12-bit serial data read into pin DI is output to
parallel output pins from D1 to D12.
Because the output form of parallel output pins is N-channel
open drain output, “H” must be written to the pin to set to in-
put mode.
OPERATION TIMING DIAGRAM
2
S
CS
CLK
DI
DO
D1
D2
DI2
(1)
(2)
DI12
DI1
DI2
1
DO1
DI1
(3)
(4)
2
DO2
DI2
3
DO3
DI3
4
DO4
DI4
5
DO5
DI5
6
DO6
DI6
1 cycle
7
DO7
DI7
DESCRIPTION OF OPERATION
(1) When power is supplied, pins DO and from D1 to D12 are
(2) At the falling edge of CS, the status of pins from D1 to D12
(3) At the falling edge of CLK, data which is loaded as above
(4) At the rising edge of CLK, 12-bit serial data is written from
(5) CLK on and after the 13th bit is neglected and writing of
(6) At the rising edge of CS, the data which is written as men-
(7) Shift register ! loads the data applied externally and the
(8) When CS rises before CLK reaches the 12th bit, the paral-
(9) Switching of I/O mode of pins from D1 to D12 is controlled
8
DO8
DI8
in undefined state. When S changes to “L”, those pins are
in high impedance state.
is loaded to shift register !.
(2) is output to pin DO as 12-bit serial data in order.
DI to shift register @.
serial data is not possible. Also, DO is put in the high im-
pedance state.
tioned in (4) is output to pins from D1 to D12.
eration and DO outputs serial data until CLK reaches the
12th bit.
by the serial data which is input to pin DI. Pins to which “H”
is written operates as input pins.
AND-tie data latched by the parallel output latch.
lel output latch latches the data which has been written to
shift register @ and outputs it to pins from D1 to D12. In
this case, shift registers ! and @ continues the shift op-
9
DO9
DI9
10
DO10 DO11 DO12
DI10
High impedance
11
DI11
12
DI12
13
(6)
(5)
M66006P/FP
12-BIT I/O EXPANDER
DO12
DO1
DO2
(6)
H
L