lc321664aj Sanyo Semiconductor Corporation, lc321664aj Datasheet - Page 7

• Manufacturer Part Number: lc321664aj
• Description: 1 Meg 65536 Words X 16 Bits Dram Fast Page Mode, Byte Write
• Manufacturer: Sanyo Semiconductor Corporation

Notes: 6)
7)
8)
9)
10) t
11) Operation is guaranteed if either t
12) These parameters are measured from the falling edge of CAS for an early-write cycle, and from the
13) t
14) t
15) t
16) Operation is guaranteed if either t
After the power is turned on, 200 µs are required after the arrival of V
memory is initialized and begins operation. In addition, before memory operation initializes,
approximately 8 cycles worth of RAS dummy cycles are required. When the on-chip refresh counter is
applied, approximately 8-cycles worth of CAS-before-RAS dummy cycles are required instead of the
RAS dummy cycles.
Measured at t
When measuring input signal timing, V
addition, rise and fall time are defined between V
Measured using an equivalent of 50 pF and one standard TTL load.
output switches to a high impedance condition.
falling edge of UW and LW for a read-write/read-modify-write cycle.
specify the operating mode. If t
pins switch to high impedance throughout the cycle. If t
t
data outputs equal information in the selected cells. If neither of the above conditions are satisfied,
output pins are in an undefined state.
the access time t
t
the access time t
t
OFF
WCS
AWD
RCD
CAC
RAD
AA
.
.
, t
(max) and t
(max) does not indicate a restrictive operating parameter but instead represents the point at which
(max) does not indicate a restrictive operating parameter but instead represents the point at which
(min) and t
CWD
, t
T
RWD
= 5 ns.
RAC
OEZ
RAC
CPWD
, t
AWD
(max) are defined as the time until output voltage can no longer be measured when
(max) is guaranteed. If t
(max) is guaranteed. If t
and t
t
CPWD
LC321664AJ, AM, AT-80
CPWD
WCS
RRH
DZC
(min), the cycle switches to a read-write/read-modify-write cycle and
or t
or t
are not restrictive operating parameters for memory in that they
t
WCS
DZO
RCH
IH
(min), the cycle switches to an early-write cycle and output
(min) and V
are satisfied.
are satisfied.
RAD
RCD
IH
and V
t
t
RCD
RAD
CWD
IL
(max), access time is determined according to
(max), access time is determined according to
IL
.
(max) are used for reference points. In
t
CWD
(min), t
CC
RWD
stabilized current before
t
RWD
(min), t
No. 4795-7/30
AWD