hm5118165tt-7 Elpida Memory, Inc., hm5118165tt-7 Datasheet - Page 5

• Manufacturer Part Number: hm5118165tt-7
• Description: 16 M Edo Dram 1-mword ? 16-bit
• Manufacturer: Elpida Memory, Inc.

Truth Table
RAS
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H to L
H to L
H to L
L
Notes: 1. H: High (inactive) L: Low (active) D: H or L
2. t
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of
LCAS
D
L
H
L
L
H
L
L
H
L
L
H
L
H
H
L
L
L
t
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However
write OPERATION and output High-Z control are done independently by each UCAS, LCAS.
ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
WCS
WCS
< 0 ns Delayed write cycle
0 ns Early write cycle
UCAS
D
H
L
L
H
L
L
H
L
L
H
L
L
H
L
H
L
L
WE
D
H
H
H
L
L*
L*
L*
L*
L*
H to L
H to L
H to L
D
D
D
D
H
*2
2
2
2
2
2
Data Sheet E0154H10
OE
D
L
L
L
D
D
D
H
H
H
L to H
L to H
L to H
D
D
D
D
H
Output
Open
Valid
Valid
Valid
Open
Open
Open
Undefined
Undefined
Undefined
Valid
Valid
Valid
Open
Open
Open
Open
Open
Lower byte Read cycle
Upper byte
Word
Lower byte Early write cycle
Upper byte
Word
Lower byte Delayed write cycle
Upper byte
Word
Lower byte Read-modify-write cycle
Upper byte
Word
Word
Word
Word
Word
Operation
Standby
RAS-only refresh cycle
CAS-before-RAS refresh cycle or
Self refresh cycle (L-version)
Read cycle (Output disabled)
HM5118165 Series
5