hm51w16165tt-7 Elpida Memory, Inc., hm51w16165tt-7 Datasheet - Page 15

• Manufacturer Part Number: hm51w16165tt-7
• Description: 16 M Edo Dram 1-mword ? 16-bit
• Manufacturer: Elpida Memory, Inc.

Self Refresh Mode (L-version)
Parameter
RAS pulse width (self refresh)
RAS precharge time (self refresh)
CAS hold time (self refresh)
Notes: 1. AC measurements assume t
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
3. Operation with the t
4. Operation with the t
5. Either t
6. Either t
7. V
8. Assumes that t
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that t
11. Assumes that t
12. Either t
13. t
14. t
15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE
16. t
17. Access time is determined by the longest among t
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device.
20 All the V
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).
reference point only; if t
exclusively by t
reference point only; if t
controlled exclusively by t
times are measured between V
recommended value shown in this table, t
and are not referred to output voltage levels.
data sheet as electrical characteristics only; if t
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t
t
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
leading edge in delayed write or read-modify-write cycles.
to the device
UCAS and LCAS cannot be staggered within the same write/read cycles.
OFF
WCS
CPW
RASP
IH
t
RWD
(min) and V
, t
(max) and t
(min), the cycle is a read-modify-write and the data output will contain data read from the
defines RAS pulse width in EDO page mode cycles.
RWD
(min), t
OED
DZO
RCH
CC
, t
or t
or t
or t
CWD
and V
CWD
, t
CDD
DZC
RRH
IL
RCD
RCD
RAD
CAC
OEZ
AWD
(max) are reference levels for measuring timing of input signals. Also, transition
SS
must be satisfied.
must be satisfied.
must be satisfied for a read cycles.
.
(max) define the time at which the outputs achieve the open circuit condition
t
CWD
pins shall be supplied with the same voltages.
and t
RCD
RAD
t
t
t
RCD
RCD
RAD
(min), and t
(max) limit insures that t
(max) limit insures that t
RCD
RAD
Data Sheet E0153H10
(max) and t
(max) and t
(max) and t
CPW
Symbol
t
t
t
AA
RASS
RPS
CHS
is greater than the specified t
.
are not restrictive operating parameters. They are included in the
T
t
RAD
= 2 ns.
IH
HM51W16165 Series, HM51W18165 Series
(max) + t
(min) and V
AWD
RAD
RCD
RCD
HM51W16165L/HM51W18165L
-5
Min
100
90
–50
+ t
+ t
t
AWD
t
RAD
AA
RAC
CAC
CAC
Max
—
—
—
(min), or t
(max) – t
(max). If t
IL
exceeds the value shown.
(max)
(max)
(max).
WCS
RAC
RAC
AA
(max) can be met, t
(max) can be met, t
-6
Min
100
110
–50
, t
t
WCS
CAC
t
t
CWD
CAC
RAD
RAD
RCD
RAD
(max), then access time is controlled
(min), the cycle is an early write cycle
and t
+ t
+ t
Max
—
—
—
or t
t
(max) limit, then access time is
CWD
AA
AA
RAD
CPA
(max).
(max).
(min), t
is greater than the maximum
.
-7
Min
100
130
–50
RCD
RAD
AWD
Max
—
—
—
(max) is specified as a
(max) is specified as a
t
AWD
µs
ns
ns
(min) and t
Unit
28, 29, 30,
Notes
31
CPW
RWD
15