LS110GXS-1CF269I LATTICE [Lattice Semiconductor], LS110GXS-1CF269I Datasheet - Page 6

• Manufacturer Part Number: LS110GXS-1CF269I
• Description: Fully Integrated 10Gbps Serializer/Deserializer Device
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Figure 2. LVDS Loopback Mode Block Diagram
LVDS Line Loopback
Line loopback is a diagnostic mode that establishes a parallel connection between the output of the deserializer
and the input to the serializer. When this mode is active, serial receive data is deserialized, and internally looped
back to the serializer. The data provided at the serializer is transmitted via the CML output. Line loopback is acti-
vated by setting the LB_P622_Enb pin to a logic low.
Mode 1: Synchronous line loopback without clock clean-up. Driving LB_P622_Enb low enables line loopback
mode. Connecting the LVDS output clock, RX_CK_LV_P/N, to REF_CK_P/N makes the loopback mode synchro-
nous. In addition, a separate reference clock is input to RX_REF_CKP/N for use by the CDR logic. The data trans-
mitted across the TX_D_P/N pins is now timed to the LVDS clock making the RX and TX data synchronous.
However, the RX_CK_LV_P/N does not require SONET/SDH tolerance in order to transmit the parallel LVDS data.
This means the data repeated on TX_D_P/N will have significant jitter.
Figure 3. Line Loopback Mode 1 Block Diagram
LB_LVDS_ENb=0
LB_LVDS_ENb=1
BIST_ENb=0
BIST_LB_SC0=0
BIST_LB_SC1=1
RX_D_LV[0..15]
RX_CK_LV_P/N
LB_P622_ENb=0
TX_D_LV[0..15]
TX_CL_LV_P/N
REF_CK_P/N
BIST_LB_SC0=0
BIST_LB_SC1=1
RX_CK_LV_P/N
TX_D_LV[0..15]
RX_D_LV[0..15]
TX_CL_LV_P/N
BIST_ENb=0
REF_CK_P/N
LVDS Clock
Bypass
LVDS Data
LVDS Data
LVDS
LVDS
RX
TX
Data
Data
RX
TX
LVDS Data
Loopback
LVDS Loopback
1
0
1
0
Mode 1
6
1
0
1
0
Loopback
Parallel
Deserializer
Serializer
Deserializer
Serializer
CMU
CMU
XPIO 110GXS Data Sheet
10G TX
10G RX
10G RX
10G TX
TX_D_N
RX_D_P
TX_D_P
RX_D_N
TX_D_N
RX_D_P
TX_D_P
RX_D_N