x24042 ETC-unknow, x24042 Datasheet

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x24042

Manufacturer Part Number
x24042
Description
Serial E2prom
Manufacturer
ETC-unknow
Datasheet

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© Xicor, 1991 Patents Pending
Preliminary Information
X24042
Pin 7 No Connect
TYPICAL FEATURES
FUNCTIONAL DIAGRAM
3849-1
2.7V to 5.5V Power Supply
Low Power CMOS
—Active Read Current Less Than 1 mA
—Active Write Current Less Than 3 mA
—Standby Current Less Than 50 A
Internally Organized 512 x 8
2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
Sixteen Byte Page Write Mode
—Minimizes Total Write Time Per Byte
Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
8 Pin Mini-DlP and 8 Pin SOIC Packages
(8) V CC
(4) V SS
(5) SDA
(6) SCL
(3) A 2
(2) A 1
(1) A 0
SLAVE ADDRESS
START
LOGIC
+COMPARATOR
STOP
REGISTER
D OUT
ACK
R/W
LOAD
Serial E
COUNTER
ADDRESS
WORD
X24042
CONTROL
LOGIC
PIN
INC
1
2
PROM
DESCRIPTION
The X24042 is a CMOS 4,096 bit serial E
internally organized 512 x 8. The X24042 features a
serial interface and software protocol allowing operation
on a simple two wire bus.
The X24042 is fabricated with Xicor’s advanced CMOS
Textured Poly Floating Gate Technology.
The X24042 utilizes Xicor’s proprietary Direct Write
cell providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
START CYCLE
XDEC
CK
H.V. GENERATION
DATA REGISTER
Characteristics subject to change without notice
& CONTROL
E
32 X 128
TIMING
2
YDEC
PROM
8
D OUT
512 x 8 Bit
3849 FHD F01
2
PROM,
TM

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x24042 Summary of contents

Page 1

... Serial E PROM DESCRIPTION The X24042 is a CMOS 4,096 bit serial E internally organized 512 x 8. The X24042 features a serial interface and software protocol allowing operation on a simple two wire bus. The X24042 is fabricated with Xicor’s advanced CMOS Textured Poly Floating Gate Technology. ...

Page 2

... An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull-Up Resistor selection graph at the end of this data sheet. Address ( unused by the X24042, however, it must be tied insure proper device operation. SS Address ( ...

Page 3

... All communications must be terminated by a stop con- dition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24042 to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus ...

Page 4

... RECEIVER START after the receipt of each subsequent eight bit word. In the read mode the X24042 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge acknowledge is detected and no stop condition is generated by the master, the X24042 will continue to transmit data ...

Page 5

... SDA bus comparing the slave address being transmit- ted with its slave address (device type and state of the A2 and A1 inputs). Upon a correct compare the X24042 outputs an acknowledge on the SDA line. Depending on HIGH the state of the R/W bit, the X24042 will execute a read ORDER or write operation. WORD ADDRESS ...

Page 6

... X24042 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the X24042 is still busy with the write operation no ACK will be returned. If the X24042 has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation ...

Page 7

... R/W bit set to one. This will be followed by an acknowledge from the X24042 and then by the eight bit word. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. ...

Page 8

... At the end of the address space (address 511) the counter “rolls over” to address 0 and the X24042 continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowl- edge and data transfer sequence. ...

Page 9

... Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. Supply Voltage Max. X24042 70 C X24042-3 +85 C X24042-2.7 +125 C 3849 PGM T02 Limits Min. Max. Units ...

Page 10

... X24042 A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times I/O Timing Levels A.C. CHARACTERISTICS LIMITS (Over recommended operating conditions, unless otherwise specified). READ & WRITE CYCLE LIMITS Symbol t SCL Clock Frequency SCL t Noise Suppression Time Constant at SCL, SDA Inputs ...

Page 11

... Write Cycle Time WR The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24042 Write Cycle Timing SCL SDA 8th BIT WORD n Notes: (5) Typical values are for and nominal supply voltage (5V) ...

Page 12

... X24042 NOTES 12 ...

Page 13

... X24042 PACKAGING INFORMATION 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. TYP. 0.010 (0.25) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.430 (10.92) 0.360 (9.14) 0.092 (2.34) DIA. NOM. PIN 1 INDEX PIN 1 0.300 (7.62) REF. SEATING PLANE 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) ...

Page 14

... X24042 PACKAGING INFORMATION 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S PIN 1 INDEX NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESIS IN MILLIMETERS) PIN 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7 0.050 (1.27) 0.010 (0.25 0.020 (0.50) 0 – 8 0.016 (0.41) 0.037 (0.937) 14 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) ...

Page 15

... Temperature Range Blank = Commercial = + Industrial = – + Military = – +125 C Package P = 8-Lead Plastic DIP S8 = 8-Lead SOIC X24042 X Blank = 8-Lead SOIC P = 8-Lead Plastic DIP S = 8-Lead SOIC X Blank = 4.5V to 5.5V + 4.5V to 5.5V, – + 3.0V to 5.5V + 3.0V to 5.5V, – ...

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