cxl1506m Sony Electronics, cxl1506m Datasheet - Page 2

• Manufacturer Part Number: cxl1506m
• Description: Cmos-ccd 1h/2h Delay Line For Pal
• Manufacturer: Sony Electronics

Pin Description (CXL1506M)
Note) Description of VG2
Pin No.
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
(Note)
Control of input signal clamp condition
0V … Sync tip clamp condition
5V … Center bias condition
IN
VG1
VG2
OUT1
V
OUT2
V
V
V
CLK
V
PC OUT
VCO IN
V
AB
V
SS
SS
SS
DD
SS
DD
SS
The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10k
In this mode the input signal is limited to the APL 50% and the maximum input signal amplitude is
at 200mVp-p.
(VCO OUT)
Symbol
(O)
I/O
—
—
—
—
—
—
O
O
O
O
O
I
I
I
I
Signal input
(Non-inverted signal)
Gate bias 1 DC output
Gate bias 2 DC input
1H signal output
(Inverted signal)
GND
2H signal output
(Inverted signal)
GND or VCO output (3fsc)
GND
Power supply (5V)
Clock input (fsc)
GND
Phase comparator output
VCO input
Power supply (5V)
Autobias DC output
GND
Description
– 2 –
> 10k (at no clamp)
40 to 500
40 to 500
> 10k
600 to 200k
Impedance [ ]
CXL1506M/N
).