la72700v Sanyo Semiconductor Corporation, la72700v Datasheet - Page 13

• Manufacturer Part Number: la72700v
• Description: Us Mts Multi Channel Television Sound Decoder
• Manufacturer: Sanyo Semiconductor Corporation

Serial Control (I
(1) Data Transfer Manual
(2) Transfer Data Format
This LSI adopts control method (I
clock) and SDA (serial data). At first, set up
SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of Bit),
and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes ‘H’, this LSI pull down
the SDA terminal. After transferred the necessary data, two terminals lead to set up and of
thus the transfer comes to close.
*1 Defined by SCL rise down SDA during ‘H’ period.
*2 Defined by SCL rise up SDA during ‘H’ period.
After transfer start condition, transfers slave address (1000000*) to SDA terminal, control data, then, stop condition
(See figure 1).
Slave address is made up of 7bits,
this LSI side, this is input operation mode), and in case of ‘H’, reading mode (As this LSI side, this is output operation
mode).
Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be canceled
the transfer dates.
*3 It is called R/W bit.
* Output 5bits data as follows;
bit8 is result of STERO DET (H: STEREO)
bit7 is result of SAP DET (H: SAP)
bit6 to bit1 are fixed to “L”
Fig.1 DATA STRUCTURE " WRITE " mode
Fig.2 DATA STRUCTURE " READ " mode
START Condition
START condition
2
C)
Slave Address
Slave Address
2
*3
C -BUS) with serial data, and controlled by two terminals which called SCL (serial
8th bit shows the direction of transferring data, if it is “L”, takes write mode (As
R/W
R/W
*1
H
L
the condition of starting data transfer, and after that, input 8 bit data to
LA72700V
ACK
ACK
Internal Data*
Control data
ACK
ACK
*2
data transfer stop condition,
STOP condition
STOP condition
No.A0015-13/16