m37280eksp Mitsumi Electronics, Corp., m37280eksp Datasheet - Page 43

• Manufacturer Part Number: m37280eksp
• Description: Single-chip 8-bit Cmos Microcomputer With Closed Caption Decoder And On-screen Display Controller
• Manufacturer: Mitsumi Electronics, Corp.

Rev. 1.0
12.6.10 Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is shown
below.
Set a slave address in the high-order 7 bits of the I
register (address 00F7
Set the ACK return mode and SCL = 100 kHz by setting “85
the I
Set “10
SCL at the HIGH.
Set a communication enable status by setting “48
control register (address 00F9
Set the address data of the destination of transmission in the high-
order 7 bits of the I
“0” in the least significant bit.
Set “F0
a START condition. At this time, an SCL for 1 byte and an ACK
clock automatically occurs.
Set transmit data in the I
this time, an SCL and an ACK clock automatically occurs.
When transmitting control data of more than 1 byte, repeat step .
Set “D0
ACK is not returned or transmission ends, a STOP condition will
be generated.
2
C clock control register (address 00FA
16
16
16
” in the I
” in the I
” in the I
2
2
2
C status register (address 00F8
C status register (address 00F8
C status register (address 00F8
2
C data shift register (address 00F6
16
2
) and “0” in the RBW bit.
C data shift register (address 00F6
16
).
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
16
).
16
16
16
) and hold the
16
). After this, if
) to generate
2
” in the I
C address
16
M37280MF–XXXSP, M37280MK–XXXSP
) and set
16
16
). At
” in
2
C
12.6.11 Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the
SCL frequency of 400 kHz, in the ACK non-return mode, using the
addressing format, is shown below.
Set a slave address in the high-order 7 bits of the I
register (address 00F7
Set the no ACK clock mode and SCL = 400 kHz by setting “25
in the I
Set “10
SCL at the HIGH.
Set a communication enable status by setting “48
control register (address 00F9
When a START condition is received, an address comparison is
made.
•When all transmitted address are“0” (general call):
•When the transmitted addresses match the address set in
•In the cases other than the above:
Set dummy data in the I
When receiving control data of more than 1 byte, repeat step
When a STOP condition is detected, the communication ends.
AD0 of the I
an interrupt request signal occurs.
ASS of the I
an interrupt request signal occurs.
AD0 and AAS of the I
to “0” and no interrupt request signal occurs.
2
16
C clock control register (address 00FA
” in the I
2
2
C status register (address 00F8
C status register (address 00F8
and ON-SCREEN DISPLAY CONTROLLER
2
C status register (address 00F8
MITSUBISHI MICROCOMPUTERS
2
16
C status register (address 00F8
2
) and “0” in the RBW bit.
C data shift register (address 00F6
16
).
M37280EKSP
16
16
16
) is set to “1” and
).
) is set to “1”and
16
) and hold the
16
2
” in the I
C address
16
) are set
16
:
).
16
2
43
C
.
”