SST49LF020A-33-4C-NHE SST [Silicon Storage Technology, Inc], SST49LF020A-33-4C-NHE Datasheet - Page 12

• Manufacturer Part Number: SST49LF020A-33-4C-NHE
• Description: 2 Mbit LPC Flash
• Manufacturer: SST [Silicon Storage Technology, Inc]

Data Sheet
TABLE 5: LPC Read Cycle
©2006 Silicon Storage Technology, Inc.
FIGURE 5: LPC Read Cycle Waveform
1. Field contents are valid on the rising edge of the present clock cycle.
Clock
Cycle
3-10
LFRAME#
11
12
13
14
15
16
17
LAD[3:0]
1
2
LCLK
CE#
ADDRESS
CYCTYPE
START
SYNC
Name
+ DIR
Field
TAR0
TAR1
DATA
DATA
TAR0
TAR1
1 Clock 1 Clock
0000b
Start
CYCTYPE
010Xb
DIR
Field Contents
+
1111 (float)
1111 (float)
LAD[3:0]
A[31:28] A[27:24]
YYYY
010X
ZZZZ
ZZZZ
0000
1111
0000
1111
1
A[23:20] A[19:16]
Load Address in 8 Clocks
then Float
then Float
Direction
then OUT
LAD[3:0]
then IN
Float
Float
OUT
OUT
OUT
OUT
IN
IN
IN
IN
Address
A[15:12]
12
Comments
LFRAME# must be active (low) for the part to respond. Only the
last start field (before LFRAME# transitions high) should be rec-
ognized.
Indicates the type of cycle. Bits 3:2 must be “01b” for memory cycle.
Bit 1 indicates the type of transfer “0” for Read. Bit 0 is reserved.
Address Phase for Memory Cycle. LPC protocol supports a 32-
bit address phase. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble fist. See Table
3 for address bits definition and
address range.
In this clock cycle, the host has driven the bus to all 1s and then
floats the bus. This is the first part of the bus “turnaround cycle.”
The SST49LF020A takes control of the bus during this cycle
The SST49LF020A outputs the value 0000b indicating that data
will be available during the next clock cycle.
This field is the least-significant nibble of the data byte.
This field is the most-significant nibble of the data byte.
In this clock cycle, the SST49LF020A has driven the bus to all
1s and then floats the bus. This is the first part of the bus “turn-
around cycle.”
The host takes control of the bus during this cycle
A[11:8]
A[7:4]
A[3:0]
1111b
TAR0
2 Clocks
Tri-State
TAR1
1 Clock
0000b
Sync
Table 4
Data Out 2 Clocks
D[3:0]
2 Mbit LPC Flash
for valid memory
D[7:4]
Data
SST49LF020A
S71206-08-000
1206 F06.0
TAR
T5.0 1206
5/06