SST49LF020A-33-4C-NHE SST [Silicon Storage Technology, Inc], SST49LF020A-33-4C-NHE Datasheet - Page 10

• Manufacturer Part Number: SST49LF020A-33-4C-NHE
• Description: 2 Mbit LPC Flash
• Manufacturer: SST [Silicon Storage Technology, Inc]

Data Sheet
DESIGN CONSIDERATIONS
SST recommends a high frequency 0.1 µF ceramic capac-
itor to be placed as close as possible between V
V
Additionally, a low frequency 4.7 µF electrolytic capacitor
from V
pin. If you use a socket for programming purposes add an
additional 1-10 µF next to each socket.
PRODUCT IDENTIFICATION
The Product Identification mode identifies the device as the
SST49LF020A and manufacturer as SST.
TABLE 2: Product Identification
MODE SELECTION
The SST49LF020A flash memory devices can operate in
two distinct interface modes: the LPC mode and the Parallel
Programming (PP) mode. The mode pin is used to set the
interface mode selection. If the mode pin is set to logic High,
the device is in PP mode. If the mode pin is set Low, the
device is in the LPC mode. The mode selection pin must be
configured prior to device operation. The mode pin is inter-
nally pulled down if the pin is left unconnected. In LPC
mode, the device is configured to its host using standard
LPC interface protocol. Communication between Host and
the SST49LF020A occurs via the 4-bit I/O communication
signals, LAD [3:0] and LFRAME#. In PP mode, the device
is programmed via an 11-bit address and an 8-bit data I/O
parallel signals. The address inputs are multiplexed in row
and column selected by control signal R/C# pin. The row
addresses are mapped to the lower internal addresses
(A
higher internal addresses (A
Device Memory Map, for address assignments.
TABLE 3: Address bits definition
©2006 Silicon Storage Technology, Inc.
Manufacturer’s ID
Device ID
SS
10-0
1. See Table 7 for multiple device selection configuration.
SST49LF020A
less than 1 cm away from the V
), and the column addresses are mapped to the
DD
to V
SS
should be placed within 5 cm of the V
1111 1111 1b
A
31
: A
23
MS-11
Address
0000H
0001H
). See Figure 4, the
DD
pin of the device.
Data
BFH
52H
1 = Memory Access
0 = Register access
DD
T2.2 1206
and
DD
10
A
22
LPC MODE
Device Operation
The LPC mode uses a 5-signal communication interface, a
4-bit address/data bus, LAD[3:0], and a control line,
LFRAME#, to control operations of the SST49LF020A.
Cycle type operations such as Memory Read and Memory
Write are defined in Intel Low Pin Count Interface Specifi-
cation, Revision 1.0. JEDEC Standard SDP (Software
Data
sequences are incorporated into the standard LPC mem-
ory cycles. See Figures 7 through 12 for command
sequences.
LPC signals are transmitted via the 4-bit Address/Data bus
(LAD[3:0]), and follow a particular sequence, depending on
whether they are Read or Write operations. LPC memory
Read and Write cycle is defined in Tables 5 and 6.
Both LPC Read and Write operations start in a similar way
as shown in Figures 5 and 6. The host (which is the term
used here to describe the device driving the memory)
asserts LFRAME# for one or more clocks and drives a start
value on the LAD[3:0] bus.
At the beginning of an operation, the host may hold the
LFRAME# active for several clock cycles, and even change
the Start value. The LAD[3:0] bus is latched every rising
edge of the clock. On the cycle in which LFRAME# goes
inactive, the last latched value is taken as the Start value.
CE# must be asserted one cycle before the start cycle to
select the SST49LF020A for Read and Write operations.
Once the SST49LF020A identify the operation as valid (a
start value of all zeros), it next expects a nibble that indi-
cates whether this is a memory Read or Write cycle. Once
this is received, the device is now ready for the Address
cycles. The LPC protocol supports a 32-bit address phase.
The SST49LF020A encode ID and register space access
in the address field. See Table 3 for address bits definition.
For Write operation the Data cycle will follow the Address
cycle, and for Read operation TAR and SYNC cycles occur
between the Address and Data cycles. At the end of every
operation, the control of the bus must be returned to the
host by a 2-clock TAR cycle.
Protection)
A
ID[3:0]
21
: A
Program
18
1
Device Memory address
2 Mbit LPC Flash
and
SST49LF020A
Erase
S71206-08-000
A
17
:A
0
commands
T3.0 1206
5/06