cxa1734s Sony Electronics, cxa1734s Datasheet
cxa1734s
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cxa1734s Summary of contents
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... US Audio Multiplexing Decoder For the availability of this product, please contact the sales office. Description The CXA1734S designed as a decoder for the Zenith TV Multi-channel System also corresponds with I C BUS. Functions include stereo 2 demodulation, SAP (Separate Audio Program) demodulation and dbx noise reduction. Various ...
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... Block Diagram —2— CXA1734S ...
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... 40k 4 80k 10k 3k 147 V 9.7k 19.4k CC 11k 4 5 1.3V 2.06k —3— CXA1734S (Ta = 25° Description 2.1V Serial data I/O pin. V > 3 < 1 Serial clock input pin. V > 3 < 1 Digital block GND. Slave address control switch. ...
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... CXA1734S Description 30k Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect ±1%) resistor between this pin and GND ...
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... 10P 4k 500 147 14.4k 500 —5— CXA1734S Description V CC Stereo block PLL loop filter integrating pin Audio multiplexing signal input pin. Set the time constant for the SAP carrier detection circuit. (Connect a 4.7 µF capacitor between this pin 50µ ...
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... CXA1734S Description Input the ( signal from SUBOUT (Pin 13). 19 Input the (SAP) signal from SAPOUT (Pin 18). Supply voltage pin. Vcc 3.3k Set the time constant for the noise detection circuit. 4k (Connect a 4.7 µF ...
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... V CC 47k 47k 20k —7— CXA1734S Description Weight the variable de- emphasis control effective value detection circuit. (Connect a 0.047 µF 36k capacitor and resistor in series between this pin and GND.) 4k 50µ Determine the restoration time constant of the ...
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... CXA1734S Description V CC Weight the VCA control effective value detection circuit. 25 (Connect a 1 µF capacitor and a 3.9 k resistor in series between this pin and GND.) Determine the restoration ...
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... Pin Pin Symbol No. voltage 28 ROUT 4.0V 29 LOUT 30 NC — Equivalent circuit 500 15k 28 500 —9— CXA1734S Description Right channel output pin. Left channel output pin. — ...
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... SCL t BUF t HD:STA t LOW t HIGH t SU:STA t HD:DAT t SU:DAT SU:STO tF tHIGH tHD;DAT tSU;DAT —12— CXA1734S Min. Typ. Max. Unit 3.0 — 5 — 1.5 — — 10 µA — — — 0 — — mA — — — ...
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... C10 0.47µ C19 100µ CXA1734S —13— R1 SDA NC 220 R2 SCL LOUT 220 DGND ROUT SAD ITIME C3 VGR VCATC 10µ R4 IREF VCAWGT 62k METAL ±1% MAININ VCAIN MAINOUT VEOUT C8 PLINT VETC 1µ R6 2.2k C11 0.047µ STFIL VEWGT 0.22µ C12 2700p C13 ...
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... STA4 120mVrms (SAPLPF) ST-L 30% ROUT output 300Hz level ST-L 30% ROUT output 3kHz level —14— CXA1734S Setting value when electrical characteristics are measured Adjustment point Test mode Adjustment contents setting Adjust as close to 490 mVrms as possible Adjust as close to 62.936 TEST-DA=1 kHz as possible Adjust to the center of the ...
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... Align STLPF with the center of the STA3 = 1 (adjustment OK) condition range free run) frequency input state, and adjust “STVCO” adjustment H (62.936 kHz) as possible. H Adjustment point Control data "SAPVCO" F Measurement data STA7 "SAPVCO1" STA8 "SAPVCO2" Adjustment point —15— CXA1734S Control data "STLPF" 3F Measurement data STA3 "STLPF" ...
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... ROUT output to the minimum. 4. Then, the adjustments in 2 and 3 above are performed to optimize the separation. 5. “WIDEBAND” Adjustment range: ±30% Adjustment bits: 6 bits Adjustment point Control data "SAPLPF" F Measurement data STA4 "SAPLPF" “SPECTRAL” Adjustment range: ±15% Adjustment bits: 6 bits —16— CXA1734S ...
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... I C BUS SAP DECODER DET MODE CONTROL FIXED VARIABLE DEEMPHASIS DEEMPHASIS (VE OUT) (VCA IN 4.7µ HPF RMS LPF DET LPF RMS DET Fig. 3. dbx-TV block —17— CXA1734S 15 SAP TELEMETRY FM 3kHz 6. =15.734kHz H 7 MATRIX (L-OUT (R-OUT) A ...
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... The currents flowing to the resistors connecting IREF (Pin 6) and ITIME (Pin 27) with GND become the reference current carrier as shown in the Fig.1. First, the SAP signal only is H carrier amplitude. NOISE discrimination is performed by detecting the —18— CXA1734S ...
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... STLPF [6] ST FILTER adj SPECTRAL [6] WIDEBAND [6] NRSW STA4 STA5 BIT4 BIT3 NOISE — STA4 STA5 BIT4 BIT3 SAPLPF — —19— CXA1734S BIT2 BIT1 BIT0 ATT [4] INPUT LEVEL adj FOMO SAPC M1 : Don't Care STA6 STA7 STA8 BIT2 BIT1 BIT0 — SAP VCO1 SAP VCO2 ...
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... MONO during SAP output.) Selection of mute ON/OFF (0: mute ON, 1: mute OFF) Selection of SAP mode mode according to the presence of SAP broadcasting Turns the input stage MVCA off when ATTSW = 1. Contents —20— CXA1734S 1: RESET 1: Stereo 1: SAP 1: Noise 1: OK range 1: OK range ...
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... DAC output test mode and STVCO adjustment mode LOUT (Pin 29): ROUT (Pin 28 ±20 ±20 the SAP block. f ±20 the ST and dbx blocks. f ±20% 0 SAP BPF OUT NR BPF OUT DA control DC level STEREO VCO oscillation frequency (4 f —21— CXA1734S ) H ...
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... When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC output is selected 1 = SAP output is selected ATTSW (1) MAIN VCA switch 0 = Normal mode 1 = MAIN VCA is passed. M1 (1) Mute the LOUT and ROUT output 0 = Mute Mute OFF —22— CXA1734S ...
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... Switch to SAP output when there is SAP discrimination. Do not switch to SAP output when there is no SAP discrimination. Switch to SAP output regardless of whether there is SAP discrimination. “MUTE” “TEST1” “TEST-DA” —23— CXA1734S SAPC=1 dbx input: “SAP” LOUT: SAP, ROUT: SAP ...
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... CXA1734S dbx Output SAPC input Lch Rch 1 MUTE L+R L+R 1 SAP SAP SAP 1 SAP L+R SAP 1 MUTE L+R L+R 1 (SAP) (SAP) (SAP) 1 (SAP) L+R (SAP MUTE ...
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... CXA1734S dbx Output SAPC input Lch Rch 0 MUTE L+R L+R 0 MUTE L+R L+R 0 MUTE L+R L+R 0 (SAP) (SAP) (SAP) 0 (SAP) L+R (SAP MUTE L+R L MUTE ...
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... DATA L L during Write HIZ DATA(n+1) ACK DATA(n+2) HIZ ACK —26— CXA1734S Stop Condition P MSB LSB HIZ HIZ ACK Sub Address ACK Data can be transferred in 8-bit units to be set as required. Sub address is incremented automatically. ...
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... SCL Address • Read timing IC output SDA SCL 9 Read timing ACK Data Read is performed during SCL rise controller) H during Read ACK MSB DATA —27— CXA1734S HIZ DATA ACK LSB ACK ...
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... LPF, SAP mode CC Measurement: L/R out 1.0 Standard level (100%) –10 0 Input level [dB] Input level vs. Distortion characteristics 2 (Stereo) Input signal: Stereo L=-R (dbx-TVNR ON), 1kHz 10 0dB=100% modulation level V =9V, 30kHz using LPF, ST mode CC Measurement point: L/R out 1.0 10 –10 10 —28— CXA1734S Standard level (100 Input level [dB] ...
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... Frequency (kHz) SAP frequency characteristics and group delay Gain 10 0 –10 Group delay 3.8f – 100 Frequency (kHz) —29— CXA1734S 70 100 100 120 ...
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... SONY CODE EIAJ CODE JEDEC CODE 30PIN SDIP (PLASTIC) + 0.4 26.9 – 0 1.778 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE MOLDING COMPOUND LEAD TREATMENT SDIP-30P-01 LEAD MATERIAL SDIP030-P-0400 PACKAGE WEIGHT —30— CXA1734S 0° to 15° EPOXY / PHENOL RESIN SOLDER/PALLADIUM PLATING COPPER ALLOY 1.8g ...