lc78684e Sanyo Semiconductor Corporation, lc78684e Datasheet

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lc78684e

Manufacturer Part Number
lc78684e
Description
Mp3 Decoder For Compact Disc Players
Manufacturer
Sanyo Semiconductor Corporation
Datasheet

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Part Number:
lc78684e-US-E
Manufacturer:
SANYO/三洋
Quantity:
20 000
Ordering number : ENN7350
Overview
The LC78684E integrates, on a single chip, CD-ROM
signal-processing functions, MP3 signal-processing func-
tions, and CD-DA shockproof signal-processing functions.
The LC78684E achieves significant power savings by
implementing signal-processing functions using hard-
wired structures.
A CD player that supports playback of MPEG audio
(MP3) recorded on CD media as well as CD-DA
shockproof playback can be implemented by combining
this IC with a CD DSP, DRAM, and audio D/A converter,
and other circuits.
Features
x MP3 Decoding Functions (MPEG audio standard
[ISO/IEC 11172-3] layer 3)
 Decodes to a digital audio signal MP3 data decoded
 Supports all bit rates, including variable bit rate
 Supports the following sampling rates.
 Can read out the MPEG header and ancillary data.
 Automatically mutes the signal on CRC errors using
 External MPEG serial data input function supports
by the CD-ROM decoder and outputs that audio
signal.
operation.
an MP3 CRC check function.
memory card playback.
MPEG1 (Fs = 32 K, 44.1 K, 48 K)
MPEG2 (Fs = 16 K, 22.05 K, 24 K)
MPEG2.5 (Fs = 8 K, 11.025 K, 12 K)
3 Any and all SANYO products described or contained herein do not have specifications that can handle
3 SANYO assumes no responsibility for equipment failures that result from using products at values that
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control
systems, or other applications whose failure can be reasonably expected to result in serious physical
and/or material damage. Consult with your SANYO representative nearest you before using any SANYO
products described or contained herein in such applications.
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
MP3 Decoder for Compact Disc Players
x CD-ROM Decoding Functions
x CD-DA Playback Functions (Shockproof support)
x Audio Signal Processing
x DRAM Interface
 Supports CD-ROM modes 1 and 2 (forms 1 and 2)
 Faithfully reproduces data stored on CD-ROM discs
 Header and sector management
 Supports playback speeds up to 4×.
 In addition to data buffering also supports C2 error
 Provides external serial output of decoded CD-ROM
 Shockproof operation for about 180 seconds (com-
 Shockproof function supports compressed, uncom-
 VCEC (variable speed) supports up to 4×-speed play-
 Serial audio signal output using LRCK, BCK, and
 Digital bass boost function (4 modes), attenuator
 Provides a base clock (384 fs) output pin for use with
 Supports the use of from 1M to 64M of external
 Supports allocation of a user area in DRAM during
using CD-ROM error correction functions.
flag buffering.
data.
pressed mode) when 64M DRAM is used.
pressed, and data through modes.
back.
DATA signals.
(I²S format, either 16-bit or 20-bit precision PCM
output, data-slot supports 16-bit, 24-bit, and 32-bit
modes)
function, and muting (f, 12 dB)
external digital filters and D/A converters.
DRAM (EDO, 2CAS, 16-bit data bus memory)
CD-ROM (MP3) playback.
LC78684E
20703RM(OT) No.7350-1/21
Continued on next page.
CMOS IC

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lc78684e Summary of contents

Page 1

... Ordering number : ENN7350 Overview The LC78684E integrates single chip, CD-ROM signal-processing functions, MP3 signal-processing func- tions, and CD-DA shockproof signal-processing functions. The LC78684E achieves significant power savings by implementing signal-processing functions using hard- wired structures player that supports playback of MPEG audio ...

Page 2

... Package: Sanyo QFP80 (14 × 14) (unit: mm)  Supply voltage Internal power supply: 1.8 V (typical) I/O power supply: 3.3 V (typical) Analog system power supply: 3.3 V (typical) MPEG Layer3 audio coding technology licensed from Fraunhofer IIS and THOMSON multimedia LC78684E Package Dimensions Unit: mm 3255-QFP80 ( 14) [LC78684E] 17.2 14 0.65 0.25 (0.83) 15.6 ...

Page 3

... CKIN generator VPRFR VCOC VCO VPDO  CKOUT PLL WOK CD-DA shockproof CNTOK (Compressed or OVF uncompressed) LRSY DATACK DATAIN C2FIN SFSY PW SBSY SBCK RESB LC78684E DRAM-I/F Data-I/F CDROM decoder CPU-I/F STREQ STCK STDAT CRCF MP3 decoder FSYNC ADLRCK ADBCK Audio I/F ADDATA No. 7350-3/21 ...

Page 4

... ADDATA 2 ADBCK 3 ADLRCK 4 C2FIN 5 TEST1 6 CKIN 7 VSS 8 CKOUT 9 TEST2 10 DVDD1 SBSY 13 SFSY 14 SBCK 15 AVDD 16 VPRFR 17 VCOC 18 VPDO 19 AVSS 20 LC78684E LC78684 (Top view) MADRS0 60 MADRS1 59 MADRS2 58 MADRS3 57 MADRS4 56 MADRS5 55 MADRS6 54 MADRS7 53 VSS 52 DVDD4 51 MADRS8 50 MADRS9 49 MADRS10 48 MADRS11 47 MADRS12 46 OEB 45 CASUB 44 CASLB ...

Page 5

... Tstg Allowable Operating Ranges at Ta Parameter Symbol V DD Supply voltage V DD High-level input voltage V IH Low-level input voltage V IL Operating frequency range Fop LC78684E Conditions     75q Pin name Conditions ...

Page 6

... V (1) OH High-level output voltage (1) OL Low-level output voltage (1) OFF Output off leakage current I (2) OFF LC78684E 1 3.0V 3 Pin name Conditions 3 ...

Page 7

... CE/CL setup time CE/CL hold time Command wait time CL H-level pulse width CL L-level pulse width Data/CL setup time Data/CL hold time Data-read access time Data-read turn-on time Data-read turn-off time : Pull-up resistor 1 K:, Output load 30 pF LC78684E Symbol min T1 500 T2 250 ...

Page 8

... Command Input/Data Output Interface Input commands (i.e. write data to the LC78684E) in the order data first and then address. The data and address are LSB first. Output data is output (i.e. read data from the LC78684E) by first issuing a read mode setup command and then performing read access operations ...

Page 9

... RASB T2 CASUB/ MADRS[12:0] Row WEB OEB MDATA[15:0] Write Cycle RASB T2 CASUB/ Row MADRS[12:0] WEB OEB T16 MDATA[15:0] LC78684E Column Column Column T10 T12 T13 Read data Read data Column Column Column T15 T14 T18 T19 ...

Page 10

... Write data hold time Refresh cycle RASB low width (refresh) RASB CASB delay (refresh) CASB setup time (refresh) CASB hold time (refresh) : These values apply when the frequency of the clock input to the CKIN pin is 16.9344 MHz. LC78684E T20 T21 T23 T24 Symbol T1 ...

Page 11

... DATA, C2FIN setup time DATA, C2FIN hold time : The figure above shows the timings when DATACK rising edge latch is used. If DATACLK falling edge latch is used, the timings are the same as those for the corresponding setup and hold signal. LC78684E T2 T3 T1h ...

Page 12

... Parameter SFSY  SBCK delay time SBCK frequency SBCK H-level pulse width SBCK L-level pulse width PW setup time PW hold time : These values apply when the frequency of the clock input to the CKIN pin is 16.9344 MHz. LC78684E SF0 SF1 Tssd T1h SBCK Fsbck PW Symbol ...

Page 13

... Full through mode is the state where the THROUGH bit (60h: bit 6) is set to 1. Parameter INPUT o OUTPUT delay time CKIN o CKOUT delay time : These values apply when the signal input to the CKIN pin is directly output from the CKOUT pin. LC78684E T1 T2 Fck Symbol ...

Page 14

... The fsck clock frequency can also be set to 2.1168 or 1.0584 MHz (typical). The values will be, in that case times the values shown. x When the STREQ pin is in input mode, the WOK, OVF, and CNTOK pins can be used instead of the STREQ, STCK, and SDAT pins. The timing specifications in this case are the same as those shown above. LC78684E T4 Fsck T1 ...

Page 15

... MP3 Serial Data Input Timing STREQ (*Output from the LC78684E) STCK STDAT STCK STDAT Performing a serial data input operation requires that a serial input command be issued. If this command has not been issued, the MP3 decoder will not operate, even if clock and data signals are applied to the STCK and STDAT pins ...

Page 16

... CKIN L-Level pulse width System Reset Input RESB pin input signal Parameter System reset pulse width : A system reset must be performed immediately after power is first applied. Design the system so that no noise appears on the reset line. LC78684E Fck Twl Twh Ratings Symbol min Fck 16 ...

Page 17

... MADRS10 O 49 MADRS9 O 50 MADRS8 O LC78684E Block CD left/right clock input Audio data output Audio bit clock output Audio left/right clock output CD C2 error flag input Test input 1 (This pin must be connected to ground during normal operation.) System clock input (16.9344 MHz) Ground External digital filter and D/A converter clock (384 fs) output Test input 2 (This pin must be connected to ground during normal operation ...

Page 18

... After first applying the power supply levels, the RESB pin must be held low for at least 1 µ 16.9344 MHz clock signal must be supplied to the CKIN pin by the CD DSP. The LC78684E does not support the implementation of an oscillator circuit using an oscillator element. LC78684E ...

Page 19

... DVDD5 MDATA15 MDATA14 VSS MDATA13 STREQ MDATA12 STDAT MDATA11 STDAT MDATA10 FSYNC CRCF DVDD6 VSS LC78684E WOK CNTOK OVF CMDOUT CMDIN CL CE INTB RESB DATAIN DATACK To CD-DSP : The CKOUT, ADLRCK, ADBCK, and ADDATA pins must be connected DSP that supports external D/A converter input. ...

Page 20

... Thermal Design x Semiconductor device failure rates are greatly accelerated by inappropriate ambient temperature and power consumption conditions. To assure the highest possible reliability, the thermal design should provide ample margins considering all possible changes in the ambient conditions. LC78684E No.7350-20/21 ...

Page 21

... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 2003. Specifications and information herein are subject to change without notice. LC78684E No.7350-21/21 ...

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