lc74776m Sanyo Semiconductor Corporation, lc74776m Datasheet - Page 3

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lc74776m

Manufacturer Part Number
lc74776m
Description
Vps/pdc Video On-screen Display
Manufacturer
Sanyo Semiconductor Corporation
Datasheet
Pin Functions
Note: *Both V
Pin no.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
DD
1 pins must be connected to power.
(CHABLK)
SYNC
OSC
SEP
Xtal
(MUTE)
CTRL1
CP
CV
OSC
VCO
VCO
SYN
SCLK
SEPC
CDLR
Xtal
CV
V
V
V
V
V
V
V
CV
SCL
SDA
RST
SIN
Pin
CS
NC
DD
DD
DD
DD
SS
SS
SS
OUT
OUT
OUT
CR
OUT
OUT
IN
IN
1
JDC
2
3
3
2
1
IN
1
IN
IN
R
Ground
Crystal oscillator
(MUTE input)
Crystal oscillator input
switching
(CHABLK)
I
LC oscillator
connections
External synchronizing
signal judgment output
Enable input
Clock input
Data input
Power supply
Charge pump output
Oscillator control voltage input
Ground
Oscillator range adjustment
Power supply (+5 V)
Video signal output
Ground
Video signal input
Video signal input
Power supply (+5 V)
Sync separator circuit input
Slice level output
Composite synchronizing
signal output
I
Background color phase
adjustment
Reset input
Power supply (+5 V)
2
2
C clock input
C bus data I/O
Function
Ground connection (digital system ground)
These pins are used either to connect the crystal and capacitors used to form an external
crystal oscillator circuit to generate the internal synchronizing signals, or to input an external
clock signal (2fsc or 4fsc). As a mask option, the Xtal
the MUTE input pin. When this pin is set low, the video output is held at the pedestal level.
(A pull-up resistor is built in and the input has hysteresis characteristics.)
Switches the mode between external clock input and crystal oscillator operation. A low level
selects crystal oscillator operation and a high level selects external clock input. As a mask
option, the CTRL1 input pin can be set to function as the CHABLK (character frame)
output. This is a 3-value output.
Clock input for the PDC/VPS data output. I
Connection for the external coil and capacitor for the oscillator used to generate
the character output dot clock
Outputs the state of the external synchronizing signal presence/absence judgment. Outputs
a high level when synchronizing signals are present.
Outputs either the crystal oscillator clock if CS and RST are low, or the VCO clock if CS
and RST are high.
(This signal is not output after a command reset.)
Enable input for the OSD serial data input.
Serial data input is enabled when this pin is low.
A pull-up resistor is built in and the input has hysteresis characteristics.
Serial data input enable pin.
A pull-up resistor is built in and the input has hysteresis characteristics.
Serial data input.
A pull-up resistor is built in and the input has hysteresis characteristics.
Composite video signal level adjustment power supply (analog system power supply)
Charge pump output. Connect a low-pass filter to this pin.
VCO oscillator control voltage input. (For data slicing)
Ground (VCO ground)
VCO oscillator range adjustment resistor connection
This pin must either be connected to ground or left open
Power supply (+5 V: VCO power supply)
Composite video signal output
Ground (analog system ground)
Composite video signal input
SECAM chrominance signal input
Power supply (+5 V: digital system power supply)
Video signal input to the internal sync separator circuit
Slice level verification pin
Internal sync separator circuit composite synchronizing signal output. The signal actually
output can be switched by MOD0 and SEL0. The DAV signal is output in the initial state.
PDC/VPS data I/O.
The I
The I
Background color phase adjustment resistor connection
System reset input.
A pull-up resistor is built in and the input has hysteresis characteristics.
Power supply (+5 V: digital system power supply)
LC74776, 74776M
2
2
C bus write address is [0111 1100].
C bus read address is [0111 1101].
2
Notes
C bus.
OUT
pin can be set to function as
No. 6018-3/35

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