lc74793 Sanyo Semiconductor Corporation, lc74793 Datasheet - Page 3

• Manufacturer Part Number: lc74793
• Description: Vps/pdc Slicer Ic
• Manufacturer: Sanyo Semiconductor Corporation

Pin Functions
Pin No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
SYNC
SEP
Xtalout
CTRL1
CP
CTRL2
VCO
VCOR
SYNin
SEP
SEPC
CDLR
Xtalin
VSS2
V
V
V
Hout
SDA
SCL
DAV
Vout
RST
Pin
NC
DD
DD
SS
OUT
OUT
1
JDG
2
IN
1
IN
Ground
Crystal oscillator connections
Crystal element switching
Data I/O
I
Clock input
I
External synchronizing signal
discrimination output
Horizontal synchronizing signal output
Ground
Charge pump output
Oscillator control voltage input
Oscillator range adjustment
Data acquisition output
Power supply (+5 V)
Sync separator circuit input
Slice level output
Composite synchronizing signal output
Vertical synchronizing signal input
Vertical synchronizing signal output
SEPin input control
Clock phase adjustment
Reset input
Power supply (+5 V)
2
2
C bus
C bus
Function
LC74793, 74793JM
Digital system ground
Connections for the crystal element and capacitors that form the crystal oscillator. Also
used for external clock input (fsc, 2fsc, or 4fsc).
Switches between external clock input mode and crystal oscillator mode. Set this pin low
for crystal oscillator, and high for external clock input.
PDC/VPS data I/O.
I
I
PDC/VPS data clock input.
I
External synchronizing signal presence/absence discrimination status output.
A high level is output when synchronizing signals are present.
This pin outputs the crystal oscillator clock when the RST pin is low.
(This reset state output can be disabled with command input.)
Horizontal synchronizing signal output
Ground. (VCO circuit ground)
Charge pump output. Connect a low-pass filter to this pin.
VCO oscillation control voltage input
VCO oscillation range adjustment resistor connection
Outputs a low level when PDC/VPS data has been discriminated
Power supply (+5 V) (VCO system power supply)
Internal sync separator circuit video signal input
Slice level verification
Internal sync separator circuit composite synchronizing signal output
Inputs the vertical synchronizing signal by integrating the SEP out pin output signal.
Applications must connect the SEP out pin to this pin through an integration circuit. If
unused, connect this pin to VDD1. (This pin is enabled when CTRL2 is high.)
Vertical synchronizing signal output
This pin outputs the VCO clock when the RST pin is low.
(This reset state output can be disabled with command input.)
Controls whether or not the VSYNC vertical synchronizing signal is input to the SEPin
input.
When low: The VSYNC signal is not input. (The internal vertical separation circuit is used.)
When high: The VSYNC signal is input.
Connection for the clock phase adjustment resistor.
System reset input.
A pull-up resistor is built in. (This input has hysteresis characteristics.)
Power supply. (+5 V: digital system power supply)
2
2
2
C bus write address: 01111100
C bus read address: 01111101
C bus
Description
No. 5966-3/24