SST29EE512-70-4C-EH SST [Silicon Storage Technology, Inc], SST29EE512-70-4C-EH Datasheet

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SST29EE512-70-4C-EH

Manufacturer Part Number
SST29EE512-70-4C-EH
Description
512 Kbit (64K x8) Page-Write EEPROM
Manufacturer
SST [Silicon Storage Technology, Inc]
Datasheet

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SST29EE512-70-4C-EH
Manufacturer:
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FEATURES:
• Single Voltage Read and Write Operations
• Superior Reliability
• Low Power Consumption
• Fast Page-Write Operation
• Fast Read Access Time
• Latched Address and Data
PRODUCT DESCRIPTION
The SST29EE512 is a 64K x8 CMOS, Page-Write
EEPROM manufactured with SST’s proprietary, high-per-
formance CMOS SuperFlash technology. The split-gate
cell design and thick-oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. The SST29EE512 writes with a single
power supply. Internal Erase/Program is transparent to
the user. The SST29EE512 conforms to JEDEC stan-
dard pin assignments for byte-wide memories.
Featuring
SST29EE512 provides a typical Byte-Write time of 39
µsec. The entire memory, i.e., 64 KByte, can be written
page-by-page in as little as 2.5 seconds, when using
interface features such as Toggle Bit or Data# Polling to
indicate the completion of a Write cycle. To protect
against inadvertent write, the SST29EE512 have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spectrum
of applications, the SST29EE512 is offered with a guar-
anteed Page-Write endurance of 10,000 cycles. Data
retention is rated at greater than 100 years.
©2005 Silicon Storage Technology, Inc.
S71060-09-000
1
– 4.5-5.5V for SST29EE512
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
– Active Current: 20 mA (typical)
– Standby Current: 10 µA (typical)
– 128 Bytes per Page, 512 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 2.5 sec (typical)
– Effective Byte-Write Cycle Time: 39 µs (typical)
– 4.5-5.5V operation: 70 ns
high
512 Kbit (64K x8) Page-Write EEPROM
performance
SST29EE512512Kb (x8) Page-Write, Small-Sector flash memories
9/05
Page-Write,
SST29EE512
the
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
• Automatic Write Timing
• End of Write Detection
• Hardware and Software Data Protection
• Product Identification can be accessed via
• TTL I/O Compatibility
• JEDEC Standard
• Packages Available
• All non-Pb (lead-free) devices are RoHS compliant
The SST29EE512 is suited for applications that require
convenient and economical updating of program, config-
uration, or data memory. For all system applications, the
SST29EE512 significantly improves performance and
reliability, while lowering power consumption. The
SST29EE512 improves flexibility while lowering the cost
for program, data, and configuration storage applications.
To meet high density, surface mount requirements, the
SST29EE512 is offered in 32-lead PLCC and 32-lead
TSOP packages. A 600-mil, 32-pin PDIP package is also
available. See Figures 1, 2, and 3 for pin assignments.
Device Operation
The SST Page-Write EEPROM offers in-circuit electrical
write capability. The SST29EE512 does not require sepa-
rate Erase and Program operations. The internally timed
Write cycle executes both erase and program transparently
to the user. The SST29EE512 has industry standard
optional Software Data Protection, which SST recom-
mends always to be enabled. The SST29EE512 is com-
patible with industry standard EEPROM pinouts and
functionality.
– Internal V
– Toggle Bit
– Data# Polling
Software Operation
– Flash EEPROM Pinouts and command sets
– 32-lead PLCC
– 32-lead TSOP (8mm x 20mm)
– 32-pin PDIP
PP
Generation
These specifications are subject to change without notice.
SSF is a trademark of Silicon Storage Technology, Inc.
Data Sheet

Related parts for SST29EE512-70-4C-EH

SST29EE512-70-4C-EH Summary of contents

Page 1

... Write cycle executes both erase and program transparently to the user. The SST29EE512 has industry standard optional Software Data Protection, which SST recom- mends always to be enabled. The SST29EE512 is com- patible with industry standard EEPROM pinouts and functionality. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ...

Page 2

... Software Data Protection. Step 2 is the byte-load cycle to a page buffer of the SST29EE512. Steps 1 and 2 use the same timing for both operations. Step internally controlled Write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage ...

Page 3

... Write cycle, otherwise the rejec- tion is valid. Data# Polling ( When the SST29EE512 is in the internal Write cycle, any attempt to read DQ of the last byte loaded during the byte- 7 load cycle will receive the complement of the true data. ...

Page 4

... Data Protection Product Identification The Product Identification mode identifies the device as the SST29EE512 and manufacturer as SST. This mode is accessed via software. For details, see Table 4, Figure 11 for the software ID entry, and Read timing diagram and Fig- ure 18 for the ID entry command sequence flowchart. ...

Page 5

... Kbit Page-Write EEPROM SST29EE512 FIGURE SSIGNMENTS FOR A11 A9 A8 A13 A14 NC WE A15 A12 FIGURE SSIGNMENTS FOR FIGURE SSIGNMENTS FOR ©2005 Silicon Storage Technology, Inc ...

Page 6

... X can but no other value Device ID = 5DH for SST29EE512 ©2005 Silicon Storage Technology, Inc. Functions To provide memory addresses. Row addresses define a page for a Write cycle. Column Addresses are toggled to load page data To output data during Read cycles and receive input data during Write cycles. ...

Page 7

... SST Manufacturer’ BFH, is read with SST29EE512 Device ID = 5DH, is read with A 6. Alternate six-byte Software Product ID Command Code Note: This product supports both the JEDEC standard three-byte command code sequence and SST’s original six-byte command code sequence. For new designs, SST recommends that the three-byte command code sequence be used. ...

Page 8

... CE#=WE#= CE#=OE#=WE#=V 50 µA CE#=OE#=WE#=V 1 µA V =GND µA V =GND to V OUT =2 =-400 µ SST29EE512 +0.5V DD +2. f=1/T Min, ILT IHT RC Max DD , WE#=V , all I/Os open OE#= Max Max -0.3V Max ...

Page 9

... Kbit Page-Write EEPROM SST29EE512 TABLE ECOMMENDED YSTEM Symbol Parameter 1 T Power-up to Read Operation PU-READ 1 T Power-up to Write Operation PU-WRITE 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7: C APACITANCE (T = 25° ...

Page 10

... Software Chip-Erase SCE 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2005 Silicon Storage Technology, Inc. SST29EE512 ARAMETERS FOR P IMING ARAMETERS 10 512 Kbit Page-Write EEPROM SST29EE512 Min Max ...

Page 11

... Kbit Page-Write EEPROM SST29EE512 ADDRESS A 15-0 CE# OE WE# HIGH-Z DQ 7-0 FIGURE EAD YCLE IMING Three-Byte Sequence for Enabling SDP ADDRESS A 15-0 5555 2AAA CE# OE# WE SW0 SW1 FIGURE 5: WE# C ONTROLLED ©2005 Silicon Storage Technology, Inc OLZ ...

Page 12

... DATA VALID T DS SW2 BYTE 0 BYTE AGE RITE YCLE IMING IAGRAM OEH BLCO D IAGRAM 12 512 Kbit Page-Write EEPROM SST29EE512 T BLCO T WC BYTE 127 1060 F06.0 T OES D D# 1060 F07.0 S71060-09-000 9/05 ...

Page 13

... Kbit Page-Write EEPROM SST29EE512 ADDRESS A 15-0 CE# T OEH OE# WE FIGURE OGGLE IT IMING ADDRESS A 14-0 5555 DQ 7-0 AA CE# OE WE# SW0 FIGURE OFTWARE ATA ©2005 Silicon Storage Technology, Inc BLCO D IAGRAM Six-Byte Sequence for Disabling Software Data Protection ...

Page 14

... BLC SW1 SW2 SW3 T D RASE IMING IAGRAM 5555 0000 IDA T BLC SW1 SW2 R EAD 14 512 Kbit Page-Write EEPROM SST29EE512 T SCE 5555 10 T BLCO SW4 SW5 1060 F10.0 0001 5D 1060 F11.0 S71060-09-000 9/05 ...

Page 15

... Kbit Page-Write EEPROM SST29EE512 Three-Byte Sequence for Software ID Exit and Reset ADDRESS A 14-0 5555 DQ 7-0 AA CE# OE WE# SW0 FIGURE 12 OFTWARE XIT AND ©2005 Silicon Storage Technology, Inc. 2AAA 5555 IDA T BLC SW1 SW2 R ESET 15 Data Sheet 1060 F12.0 ...

Page 16

... V LT (0.4 V) for a logic “0”. Measurement reference points for ILT (0.8 V). Input rise and fall times (10 EFERENCE AVEFORMS TO TESTER LOW 16 512 Kbit Page-Write EEPROM SST29EE512 V HT OUTPUT V LT 1060 F13.0 ↔ 90%) are <10 ns. Note Test HT HIGH Test ...

Page 17

... Kbit Page-Write EEPROM SST29EE512 See Figure 17 FIGURE 15 RITE LGORITHM ©2005 Silicon Storage Technology, Inc. Start Software Data Protect Write Command Set Page Address Set Byte Address = 0 Load Byte Data Increment Byte Address By 1 Byte No Address = 128? Yes Wait T BLCO ...

Page 18

... Kbit Page-Write EEPROM Toggle Bit Page-Write Initiated Read a byte from page Read same byte No Does DQ 6 match? Yes Write Completed 18 SST29EE512 Data# Polling Page-Write Initiated Read DQ 7 (Data for last byte loaded true data? Yes Write Completed 1060 F16.0 S71060-09-000 ...

Page 19

... Kbit Page-Write EEPROM SST29EE512 Software Data Protect Enable Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Load 0 to 128 Bytes of page data Wait T BLCO Wait T WC SDP Enabled FIGURE 17 OFTWARE ATA © ...

Page 20

... Silicon Storage Technology, Inc. Software Product ID Exit & Reset Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: F0H Address: 5555H Pause 10 µs Return to normal operation C F OMMAND LOWCHARTS 20 512 Kbit Page-Write EEPROM SST29EE512 1060 F18.0 S71060-09-000 9/05 ...

Page 21

... Kbit Page-Write EEPROM SST29EE512 FIGURE 19 OFTWARE HIP ©2005 Silicon Storage Technology, Inc. Software Chip-Erase Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: AAH Address: 5555H Write data: 55H ...

Page 22

... XX XXXX - XXX Valid combinations for SST29EE512 SST29EE512-70-4C-NH SST29EE512-70-4C-EH SST29EE512-70-4C-NHE SST29EE512-70-4C-EHE SST29EE512-70-4I-NH SST29EE512-70-4I-EH SST29EE512-70-4I-NHE SST29EE512-70-4I-EHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ...

Page 23

... Kbit Page-Write EEPROM SST29EE512 PACKAGING DIAGRAMS TOP VIEW .495 .485 .453 Optional .447 Pin #1 .048 Identifier .042 .042 .048 .595 .553 .585 .547 .050 BSC Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). ...

Page 24

... LEAD HIN MALL UTLINE SST ACKAGE ODE ©2005 Silicon Storage Technology, Inc. 18.50 18.30 20.20 19.80 (TSOP ACKAGE 512 Kbit Page-Write EEPROM SST29EE512 1.05 0.95 0.50 BSC 8.10 0.27 7.90 0.17 0.15 0.05 DETAIL 1.20 max. 0.70 0.50 1mm 32-tsop-EH-7 S71060-09-000 0˚- 5˚ 9/05 ...

Page 25

... Kbit Page-Write EEPROM SST29EE512 Pin #1 Identifier .075 .065 Base Plane Seating Plane .050 .015 .080 .065 .070 .045 Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. ...

Page 26

... Data Book 07 • WH package is no longer offered • Removed the SST29EE512 90 ns Read Access Time • Removed the SST29LE512 200 ns Read Access Time • Removed the SST29VE512 250 ns Read Access Time • Clarified I Write to be Program and Erase in Table 6 on page 9 ...

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