IDT72V223 IDT [Integrated Device Technology], IDT72V223 Datasheet - Page 3

• Manufacturer Part Number: IDT72V223
• Description: 3.3 VOLT HIGH-DENSITY SUPERSYNC NARROW BUS FIFO
• Manufacturer: IDT [Integrated Device Technology]

which can assume either an 18-bit or a 9-bit width as determined by the state
of external control pins Input Width (IW) and Output Width (OW) during the Master
Reset cycle.
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
WCLK when WEN is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the WEN input should be tied to its active state, (LOW).
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
DESCRIPTION (CONTINUED)
PIN CONFIGURATIONS (CONTINUED)
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
Each FIFO has a data input port (D
The input port can be selected as either a Synchronous (clocked) interface,
The output port can be selected as either a Synchronous (clocked) interface,
A
B
C
D
H
K
E
F
G
J
ASYW
WCLK
WEN
D17
D13
D11
D16
D8
D6
D5
1
MRS
SEN
PRS
D14
D12
D15
IW
D9
D7
2
D4
n
) and a data output port (Q
A1 BALL PAD CORNER
FWFT/SI
FF/IR
V
V
V
D10
V
BGA: 1mm pitch, 11mm x 11mm (BC100-1, order code: BC)
LD
D3
D2
CC
CC
CC
CC
3
GND
GND
GND
PAF
GND
V
OW
V
D0
D1
4
CC
CC
n
), both of
FSEL0
TRST
GND
GND
GND
GND
TMS
V
V
HF
CC
5
CC
TM
TOP VIEW
3
NARROW BUS FIFO
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the REN input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, and the OE input used
to provide three-state control of the outputs, Qn.
to f
of the one clock input with respect to the other.
Standard mode and First Word Fall Through (FWFT) mode.
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
to the data output lines after three transitions of the RCLK signal. A REN does
FSEL1
GND
GND
GND
GND
TCK
TDI
V
V
BE
TM
MAX
The frequencies of both the RCLK and the WCLK signals may vary from 0
In IDT Standard mode, the first word written to an empty FIFO will not appear
In FWFT mode, the first word written to an empty FIFO is clocked directly
CC
There are two possible timing modes of operation with these devices: IDT
CC
6
NARROW BUS FIFO
with complete independence. There are no restrictions on the frequency
ASYR
GND
GND
GND
GND
TDO
V
V
Q0
IP
CC
CC
7
PFM
PAE
V
V
V
V
V
Q1
Q3
Q2
CC
CC
CC
CC
CC
8
EF/OR
Q14
Q16
Q13
Q11
RM
RT
Q5
Q9
Q4
9
COMMERCIAL AND INDUSTRIAL
4666 drw02b
RCLK
REN
Q17
Q12
Q10
Q15
OE
Q8
Q7
Q6
10
TEMPERATURE RANGES