IDT72V223 IDT [Integrated Device Technology], IDT72V223 Datasheet - Page 29

• Manufacturer Part Number: IDT72V223
• Description: 3.3 VOLT HIGH-DENSITY SUPERSYNC NARROW BUS FIFO
• Manufacturer: IDT [Integrated Device Technology]

Q
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
5. There must be at least two words written to and two words read from the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
WCLK
RCLK
0
WEN
REN
- Q
PAE
PAF
1
= first word written to the FIFO after Master Reset, W
HF
EF
RT
If x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263,
16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293.
If both x9 Input and x9 Output bus Widths are selected, D = 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384
for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293.
n
t
ENS
W
x
t
t
A
ENH
t
ENS
t
RTS
t
RTS
Figure 11. Retransmit Timing (IDT Standard Mode)
2
= second word written to the FIFO after Master Reset.
t
t
t
ENH
REF
t
HF
SKEW2
1
W
x+1
TM
29
NARROW BUS FIFO
2
t
PAFS
TM
1
NARROW BUS FIFO
t
REF
t
ENS
2
t
t
A
PAES
COMMERCIAL AND INDUSTRIAL
W
1
TEMPERATURE RANGES
(3)
t
t
A
ENH
4666 drw14
W
2
(3)