IDT72V205 IDT [Integrated Device Technology], IDT72V205 Datasheet - Page 20

• Manufacturer Part Number: IDT72V205
• Description: 3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. t
2. LD = HIGH.
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
NOTES:
1. t
2. LD = HIGH.
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Q
D
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
D
WCLK
RCLK
WCLK
0
0
WEN
0
RCLK
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion time may be delayed an extra WCLK cycle.
edge of RCLK and the rising edge of WCLK is less than t
REN
SKEW1
SKEW1
-
WEN
- Q
- D
REN
D
FF
OE
FF
17
17
17
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus t
LOW
DATA IN OUTPUT REGISTER
t
ENS
NO WRITE
t
SKEW1
1
Figure 25. Write Cycle Timing with Double Register-Buffered FF (IDT Standard Mode)
t
(1)
SKEW1
t
CLKH
Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)
t
ENH
(1)
t
A
1
t
CLK
t
SKEW1
CLKL
. then the FF deassertion may be delayed an extra WCLK cycle.
2
t
WFF
2
t
DS
t
WFF
20
TM
Wd
t
DATA READ
WFF
DATA IN VALID
t
ENS
t
DS
t
ENS
NO WRITE
t
SKEW1
t
ENH
(1)
t
t
ENH
DH
t
A
t
WFF
1
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WFF
RFF
NO OPERATION
. If the time between the rising
. If the time between the rising
NEXT DATA READ
DATA WRITE
2
t
WFF
4294 drw 25
4294 drw 24
t
DS