IDT72V205 IDT [Integrated Device Technology], IDT72V205 Datasheet - Page 12

• Manufacturer Part Number: IDT72V205
• Description: 3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. t
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
NOTES:
1. When t
2. The first word is available the cycle after EF goes HIGH, always.
3. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Q
Q
D
edge of WCLK and the rising edge of RCLK is less than t
Latency Timing applies only at the Empty Boundary (EF = LOW).
SKEW1
0
WCLK
0
0
WCLK
RCLK
RCLK
- Q
WEN
REN
WEN
- Q
- D
REN
OE
OE
EF
EF
17
17
17
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising
SKEW1
minimum specification, t
t
t
ENS
ENS
t
DS
Figure 8. First Data Word Latency with Single Register-Buffered EF (IDT Standard Mode)
Figure 7. Read Cycle Timing with Single Register-Buffered EF (IDT Standard Mode)
FRL
D
t
OLZ
0
(maximum) = t
(first valid write)
t
t
ENH
CLKH
t
SKEW1
t
REF
t
A
CLK
t
OE
SKEW1
t
OLZ
+ t
, then EF may not change state until the next RCLK edge.
t
SKEW1
CLK
t
FRL
NO OPERATION
. When t
(1)
t
SKEW1
D
1
t
t
REF
CLKL
SKEW1
t
ENS
(1)
12
< minimum specification, t
TM
t
OE
VALID DATA
D
t
A
2
FRL
t
REF
(maximum) = either 2*t
t
OHZ
D
COMMERCIAL AND INDUSTRIAL
0
D
t
A
3
CLK
TEMPERATURE RANGES
+ t
SKEW1
or t
CLK
D
4294 drw 08
+ t
1
D
4294 drw 07
SKEW1
4
. The