IDT72251 IDT [Integrated Device Technology], IDT72251 Datasheet - Page 6

• Manufacturer Part Number: IDT72251
• Description: CMOS SyncFIFOO 8192 X 9
• Manufacturer: IDT [Integrated Device Technology]

IDT72251 CMOS SyncFIFO
8192 x 9
at one time. One or two offset registers can be written and then
by bringing the Write Enable 2/Load (WEN2/
FIFO is returned to normal read/write operation. When the
Write Enable 2/Load (WEN2/
Enable 1 (
is written.
output lines when the Write Enable 2/Load (WEN2/
set low and both Read Enables (
Data can be read on the LOW-to-HIGH transition of the read
clock (RCLK).
to the offset registers.
OUTPUTS:
further write operation, when the device is full. If no reads are
performed after Reset (
after 8192 writes for the IDT72251.
to-HIGH transition of the write clock (WCLK).
inhibiting further read operations, when the read pointer is
equal to the write pointer, indicating the device is empty.
LOW-to-HIGH transition of the read clock (RCLK).
Programmable Almost-Full Flag (
FIFO reaches the Almost-Full condition. If no reads are
performed after Reset (
Flag (
The offset “m” is defined in the Full offset registers.
Almost-Full Flag (
with respect to the LOW-to-HIGH transition of the write clock
(WCLK).
Programmable Almost-Empty Flag (
the read pointer is "n+1" locations less than the write pointer.
The offset "n" is defined in the Empty offset registers. If no
reads are performed after Reset the Programmable Almost-
Empty Flag (
Almost-Empty Flag (
synchronized with respect to the LOW-to-HIGH transition of
the read clock (RCLK).
data.
However, writing all offset registers does not have to occur
The contents of the offset registers can be read on the
A read and write should not be performed simultaneously
Full Flag (
The Full Flag (
Empty Flag (
The Empty Flag (
Programmable Almost-Full Flag (
If there is no Full offset specified, the Programmable
The Programmable Almost-Full Flag (
Programmable Almost-Empty Flag (
If there is no Empty offset specified, the Programmable
The Programmable Almost-Empty Flag (
Data Outputs (Q
PAF
WEN1
) will go LOW after 8192 writes for the IDT72251.
PAE
FF FF
) — The Full Flag (
) is LOW, the next offset register in sequence
FF
EF EF
) will go HIGH after "n+1" for the IDT72251.
PAF
) is synchronized with respect to the LOW-
) — The Empty Flag (
0
EF
PAE
) will go LOW at Full-7 words.
- Q
) is synchronized with respect to the
RS
RS
) will go LOW at Empty+7 words.
8
) — Data outputs for a 9-bit wide
), the Full Flag (
), the Programmable Almost-Full
LD
) pin is set LOW, and Write
REN1
PAF
FF
PAE
) will go LOW, inhibiting
) will go LOW when the
,
PAF
REN2
) will go LOW when
EF
LD
FF
) is synchronized
PAF
PAF
) will go LOW,
) are set LOW.
PAE
) pin HIGH, the
PAE
) will go LOW
) — The
) — The
LD
PAE
) pin is
) is
5.14
NOTE:
1. The same selection sequence applies to reading from the registers.
TABLE 1: STATUS FLAGS
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
8
8
8
8
LD
and
transition of RCLK.
0
0
1
1
NUMBER OF WORDS
(n+1) to (8192-(m+1)
(8192-m)
REN2
Figure 3. Offset Register Location and Default Values
7
7
WEN1
IN FIFO
1 to n
0
1
0
1
8192
are enabled and read is performed on the LOW-to-HIGH
0
(2)
(1)
to 8191
Figure 2. Write Offset Register
4
4
WCLK
72251 — 8192 x 9-BIT
(1)
Default Value 007H
Default Value 007H
Empty Offset (LSB)
Full Offset (LSB)
FF
H
H
H
H
L
COMMERCIAL TEMPERATURE RANGES
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Into FIFO
No Operation
PAF
H
H
H
L
L
Selection
(MSB)
(MSB)
00000
00000
PAE
H
H
H
L
L
EF
H
H
H
H
L
REN1
6
0
0
0
0