IDT72251 IDT [Integrated Device Technology], IDT72251 Datasheet
IDT72251
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IDT72251 Summary of contents
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... The IDT72251 SyncFIFO is a very high-speed, low- power First-In, First-Out (FIFO) memory with clocked read and write controls. The IDT72251 has a 8192 x 9-bit memory array. This FIFO is applicable for a wide variety of data buffering needs such as graphics, local area networks and FUNCTIONAL BLOCK DIAGRAM ...
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... IDT72251 CMOS SyncFIFO 8192 x 9 PIN CONFIGURATION PIN DESCRIPTIONS Symbol Name I Data Inputs I Data inputs for a 9-bit bus Reset I When FF power-up. WCLK Write Clock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted. ...
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... IDT72251 CMOS SyncFIFO 8192 x 9 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with Respect to GND T Operating A Temperature T Temperature BIAS Under Bias T Storage STG Temperature I DC Output OUT Current NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only ...
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... IDT72251 CMOS SyncFIFO 8192 ELECTRICAL CHARACTERISTICS (Commercial 10 Symbol Parameter f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock HIGH Time CLKH t Clock LOW Time CLKL t Data Set-up Time DS t Data Hold Time DH t Enable Set-up Time ...
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... IDT72251 CMOS SyncFIFO 8192 x 9 SIGNAL DESCRIPTIONS INPUTS: Data — Data inputs for 9-bit wide data CONTROLS Reset ( ) — Reset is accomplished whenever the Reset input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is ...
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... FIFO reaches the Almost-Full condition reads are RS performed after Reset ( ), the Programmable Almost-Full PAF Flag ( ) will go LOW after 8192 writes for the IDT72251. The offset “m” is defined in the Full offset registers. If there is no Full offset specified, the Programmable PAF Almost-Full Flag ( ) will go LOW at Full-7 words. ...
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... IDT72251 CMOS SyncFIFO 8192 REN1, REN2 WEN1 LD (1) WEN2/ EF PAE , FF PAF , NOTES Holding WEN2/ HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/ a load enable for the programmable flag offset registers. ...
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... IDT72251 CMOS SyncFIFO 8192 x 9 WCLK WEN1 WEN2/ (If Applicable) FF SKEW1 (1) t RCLK REN1 , REN2 NOTE the minimum time between a rising RCLK edge and a rising WCLK edge for SKEW1 the rising edge of RCLK and the rising edge of WCLK is less than t ...
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... IDT72251 CMOS SyncFIFO 8192 x 9 RCLK t ENH t ENS REN1 , REN2 WCLK WEN1 WEN2 NOTE the minimum time between a rising WCLK edge and a rising RCLK edge for SKEW1 the rising edge of RCLK and the rising edge of WCLK is less than t ...
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... IDT72251 CMOS SyncFIFO 8192 x 9 WCLK WEN1 WEN2 (If Applicable) RCLK EF REN1, REN2 NOTE: 1. When t minimum specification, t SKEW1 FRL When t < minimum specification, t SKEW1 FRL The Latency Timings apply only at the Empty Boundary ( (First Valid 0 t ENS ...
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... IDT72251 CMOS SyncFIFO 8192 WRITE WCLK t SKEW1 WEN1 WEN2 (If Applicable) RCLK t ENH t ENS REN1 , REN2 LOW DATA IN OUTPUT REGISTER WFF WFF t A DATA READ Figure 8. Full Flag Timing 5.14 COMMERCIAL TEMPERATURE RANGES NO WRITE SKEW1 ...
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... IDT72251 CMOS SyncFIFO 8192 x 9 WCLK t DS DATA WRITE ENH t ENS WEN1 t ENH t ENS WEN2 (If Applicable) t SKEW1 RCLK EF REN1 , REN2 LOW DATA IN OUTPUT REGISTER 0 8 NOTE: 1. When t minimum specification, t SKEW1 FRL When t < minimum specification, t SKEW1 The Latency Timings apply only at the Empty Boundary ( ...
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... RCLK REN1, REN2 NOTES: 1. PAF offset = m. 2. 8192 - m words in FIFO IDT72251 the minimum time between a rising RCLK edge and a rising WCLK edge for SKEW2 edge of RCLK and the rising edge of WCLK is less than write is performed on this rising edge of the write clock, there will be Full - (m-1) words in the FIFO when ...
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... IDT72251 CMOS SyncFIFO 8192 CLKL CLKH WCLK t ENS WEN1 t ENS WEN2 (If Applicable) PAE n words in FIFO t SKEW2 RCLK REN1 , REN2 NOTES: 1. PAE offset = the minimum time between a rising WCLK edge and a rising RCLK edge for SKEW2 edge of WCLK and the rising edge of RCLK is less than t 3 ...
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... IDT72251 CMOS SyncFIFO 8192 CLK t t CLKH CLKL WCLK t ENS LD t ENS WEN1 PAE OFFSET (LSB) t CLK t t CLKH CLKL RCLK t ENS LD t ENS REN1, REN2 DATA IN OUTPUT REGISTER ENH t DH PAE OFFSET PAF OFFSET ...
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... IDT72251 CMOS SyncFIFO 8192 x 9 OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION - A single IDT72251 may be used when the application requirements are for 8192 words or less. When the IDT72251 Single Device WRITE CLOCK (WCLK) WRITE ENABLE 1 ( WRITE ENABLE 2/LOAD (WEN2/ DATA IN (D FULL FLAG ( PROGRAMMABLE ALMOST FULL ( Figure 14 ...
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... IDT72251 CMOS SyncFIFO 8192 x 9 DEPTH EXPANSION - The IDT72251 can be adapted to applications when the requirements are for greater than 8192 words. The existence of two enable pins on the read and write port allow depth expansion. The Write Enable 2/Load pin is used as a second write enable in a depth expansion configu- ration thus the Programmable flags are set to the default values ...