IDT72211 IDT [Integrated Device Technology], IDT72211 Datasheet - Page 7
![no-image](/images/no-image-200.jpg)
IDT72211
Manufacturer Part Number
IDT72211
Description
CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
Manufacturer
IDT [Integrated Device Technology]
Datasheet
1.IDT72211.pdf
(19 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72211-L15J
Manufacturer:
IDT
Quantity:
20 000
Part Number:
IDT72211L-15J
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
IDT72211L10J
Manufacturer:
IDT
Quantity:
12 388
Company:
Part Number:
IDT72211L10J
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72211L10J8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72211L10JG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72211L10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72211L10PF-L25PF
Manufacturer:
IDT
Quantity:
250
Company:
Part Number:
IDT72211L10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72211L15J
Manufacturer:
IDT
Quantity:
1 831
Part Number:
IDT72211L15J
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
IDT72211L15JI
Manufacturer:
IDT
Quantity:
1 831
Company:
Part Number:
IDT72211L15PF
Manufacturer:
IDT
Quantity:
2
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
at one time. One or two offset registers can be written and then
by bringing the Write Enable 2/Load (WEN2/
FIFO is returned to normal read/write operation. When the
Write Enable 2/Load (WEN2/
Enable 1 (
is written.
output lines when the Write Enable 2/Load (WEN2/
set low and both Read Enables (
Data can be read on the LOW-to-HIGH transition of the read
clock (RCLK).
to the offset registers.
8
8
8
8
8
8
8
8
However, writing all offset registers does not have to occur
The contents of the offset registers can be read on the
A read and write should not be performed simultaneously
7
7
WEN1
72421 - 64 x 9-BIT
72221 - 1024 x 9-BIT
Empty Offset (LSB) Reg.
Default Value 007H
Full Offset (LSB) Reg.
Default Value 007H
6
6 5
5
Empty Offset (LSB) Reg.
Full Offset (LSB) Reg.
Default Value 007H
) is LOW, the next offset register in sequence
Default Value 007H
1
1
LD
(MSB)
(MSB)
00
00
) pin is set LOW, and Write
REN1
0
0
0
0
0
0
0
0
Figure 3. Offset Register Location and Default Values
,
REN2
8
8
8
8
8
8
8
8
LD
) are set LOW.
) pin HIGH, the
7
7
7
7
LD
72201 - 256 x 9-BIT
72231 - 2048 x 9-BIT
Empty Offset (LSB) Reg.
Default Value 007H
Full Offset (LSB) Reg.
Default Value 007H
Empty Offset (LSB) Reg.
Default Value 007H
Full Offset (LSB) Reg.
Default Value 007H
) pin is
5.07
NOTE:
1. The same selection sequence applies to reading from the registers.
LD
and
transition of RCLK.
0
0
1
1
2
2
REN2
(MSB)
(MSB)
WEN1
000
000
0
1
0
1
are enabled and read is performed on the LOW-to-HIGH
Figure 2. Write Offset Register
0
0
0
0
0
0
0
0
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WCLK
8
8
8
8
8
8
8
8
(1)
7
7
7
7
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Into FIFO
No Operation
72241 - 4096 x 9-BIT
72211 - 512 x 9-BIT
Default Value 007H
Default Value 007H
Empty Offset (LSB)
Default Value 007H
Empty Offset (LSB)
Default Value 007H
Full Offset (LSB)
Full Offset (LSB)
Selection
3
3
(MSB)
(MSB)
0000
0000
1
1
2655 drw 04
2655 drw 05
(MSB)
(MSB)
REN1
0
0
7
0
0
0
0
0
0
0
0
0