16C6N4 RENESAS [Renesas Technology Corp], 16C6N4 Datasheet - Page 2

• Manufacturer Part Number: 16C6N4
• Description: Renesas MCU
• Manufacturer: RENESAS [Renesas Technology Corp]

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ03B0003-0240
Under development
This document is under development and its contents are subject to change.
1.2 Performance Overview
Table 1.1 Functions and Specifications for M16C/6N Group (M16C/6N4)
NOTES:
option: All options are on request basis.
CPU
Peripheral
Function
Electrical
Characteristics
Flash Memory Programming and erasure voltage 3.0 ± 0.3 V or 5.0 ± 0.5 V
Version
I/O
Characteristics Output current
Operating Ambient Temperature
Device Configuration
Package
Table 1.1 lists the Functions and Specifications for M16C/6N Group (M16C/6N4).
1. I
2. IEBus is a trademark of NEC Electronics Corporation.
2
Aug 25, 2006
C-bus is a trademark of Koninklijke Philips Electronics N.V.
Number of fundamental
instructions
Minimum instruction
execution time
Operating mode
Address space
Memory capacity
Ports
Multifunction timers
Serial interfaces
A/D converter
D/A converter
DMAC
CRC calculation circuit
CAN module
Watchdog timer
Interrupts
Clock generation circuits
Oscillation-stopped detector Main clock oscillation stop and re-oscillation detection function
Supply voltage
Consumption Mask ROM
current
Programming and erasure endurance 100 times
I/O withstand voltage
Item
page 2 of 88
Flash memory 22 mA (f(BCLK) = 24 MHz,
Mask ROM
Flash memory 0.8 µA (Stop mode, Topr = 25°C)
91 instructions
41.7 ns (f(BCLK) = 24 MHz,
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
Single-chip, memory expansion, and microprocessor modes
1 Mbyte
Refer to Table 1.2 Product Information
Input/Output: 87 pins, Input: 1 pin
Timer A: 16 bits ✕ 5 channels
Timer B: 16 bits ✕ 6 channels
Three-phase motor control circuit
3 channels
1 channel
10-bit A/D converter: 1 circuit, 26 channels
8 bits ✕ 2 channels
2 channels
CRC-CCITT
2 channels with 2.0B specification
15 bits ✕ 1 channel (with prescaler)
Internal: 31 sources, External: 9 sources
Software: 4 sources, Priority levels: 7 levels
4 circuits
• Main clock oscillation circuit (*)
• Sub clock oscillation circuit (*)
• On-chip oscillator
• PLL frequency synthesizer
VCC = 3.0 to 5.5 V (f(BCLK) = 24 MHz, VCC = 4.2 to 5.5 V (f(BCLK) = 20 MHz,
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
20 mA (f(BCLK) = 24 MHz,
PLL operation, no division)
PLL operation, no division)
3 µA (f(BCLK) = 32 kHz, Wait mode, Oscillation capacity Low)
5.0 V
5 mA
-40 to 85°C
CMOS high-performance silicon gate
100-pin molded-plastic QFP, LQFP
Clock synchronous, UART, I
Clock synchronous
(*) Equipped with on-chip feedback resistor
Normal-ver.
Specification
2
50.0 ns (f(BCLK) = 20 MHz,
18 mA (f(BCLK) = 20 MHz,
PLL operation, no division)
20 mA (f(BCLK) = 20 MHz,
PLL operation, no division)
5.0 ± 0.5 V
T version: -40 to 85°C
V version: -40 to 125°C (option)
C-bus
(1)
, IEBus
T/V-ver.
(2)
1. Overview