74HC/HCT192 Philips Semiconductors (Acquired by NXP), 74HC/HCT192 Datasheet
74HC/HCT192
Related parts for 74HC/HCT192
74HC/HCT192 Summary of contents
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... DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT192 Presettable synchronous BCD decade up/down counter Product specification File under Integrated Circuits, IC06 ...
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... Output capability: standard I category: MSI CC GENERAL DESCRIPTION The 74HC/HCT192 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT192 are synchronous BCD up/down counters. Separate up/down clocks, CP respectively, simplify operation ...
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... GND ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information” December 1990 CONDITIONS , pF notes 1 and where 1 Product specification 74HC/HCT192 TYPICAL HC HCT MHz 3.5 3 UNIT ...
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... LOW) terminal count up (carry) output (active LOW) terminal count down (borrow) output (active LOW) asynchronous master reset input (active HIGH) data inputs positive supply voltage Fig.2 Logic symbol. 4 Product specification 74HC/HCT192 Fig.3 IEC logic symbol. ...
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... Fig.4 Functional diagram. 5 Product specification 74HC/HCT192 OUTPUTS ...
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... BCD seven; count up to eight, nine, terminal count up, zero, one and two; count down to one, zero, terminal count down, nine, eight, and seven. December 1990 Fig.5 Typical clear, load and count sequence. Fig.6 Logic diagram. 6 Product specification 74HC/HCT192 ...
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... Product specification 74HC/HCT192 . TEST CONDITIONS UNIT WAVEFORMS 125 (V) 325 ns 2.0 Fig.7 65 4.5 55 6.0 190 ns 2.0 Fig.8 38 4.5 32 6.0 190 ns 2.0 Fig.8 38 4.5 32 6.0 325 ns 2.0 Fig ...
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... Product specification 74HC/HCT192 TEST CONDITIONS UNIT WAVEFORMS 125 (V) ns 2.0 Fig.7 4.5 6.0 ns 2.0 Fig.7 4.5 6.0 ns 2.0 Fig.10 4.5 6.0 ns 2.0 Fig.9 4.5 6.0 ns 2.0 Fig.9 4.5 6.0 ns 2.0 Fig.10 4.5 6.0 ns 2.0 Fig.11 note: 4 ...
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... The value of additional quiescent supply current ( I To determine I per input, multiply this value by the unit load coefficient shown in the table below. CC INPUT UNIT LOAD COEFFICIENT 0.65 MR 1.05 December 1990 ) for a unit load given in the family specifications Product specification 74HC/HCT192 . ...
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... Product specification 74HC/HCT192 TEST CONDITIONS UNIT WAVEFORMS 125 ( 4.5 Fig 4.5 Fig 4.5 Fig 4.5 Fig 4.5 Fig. 4.5 Fig 4.5 Fig ...
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... Waveforms showing the parallel load input (PL) and data (D removal time to clock input (CP December 1990 , output (Q ) propagation delays, the clock pulse width and terminal count output ( Product specification 74HC/HCT192 , TC ) propagation delays output propagation delays and PL n ...
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... M I Fig.12 Waveforms showing the data input (D terminal count outputs (TC December 1990 ) to parallel load input (PL) set-up and hold times parallel load input (PL) and the master reset input (MR) to the propagation delays Product specification 74HC/HCT192 propagation delays ...
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... HCT 1 GND Fig.13 Waveforms showing the CP APPLICATION INFORMATION Fig.14 Cascaded up/down counter with parallel load. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines” December 1990 hold times Product specification 74HC/HCT192 ...