DS092 Xilinx Corp., DS092 Datasheet - Page 2

• Manufacturer Part Number: DS092
• Description: Xc2c64 Coolrunner-ii CPLD
• Manufacturer: Xilinx Corp.

XC2C64 CoolRunner-II CPLD
Fast Zero Power Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
Fast Zero Power™ (FZP), a design technique that makes
use of CMOS technology in both the fabrication and design
methodology. FZP design technology employs a cascade of
CMOS gates to implement sum of products instead of tradi-
tional sense amplifier methodology. Due to this technology,
Xilinx CoolRunner-II CPLDs achieve both high performance
and low power operation.
Supported I/O Standards
The CoolRunner-II 64 macrocell features both LVCMOS
and LVTTL I/O implementations. See
dard voltages. The LVTTL I/O standard is a general purpose
EIA/JEDEC standard for 3.3V applications that use an
Table 2: I
2
Notes:
1.
Typical -5, -7.5 I
Typical -4 I
16-bit up/down, resettable binary counter (one counter per function block).
CC
CC
vs Frequency (LVCMOS 1.8V T
(mA)
CC
(mA)
0.015
0
15
10
20
5
0
0
1.85
25
Table 1
50
3.69
for I/O stan-
A
Figure 1: I
50
= 25°C)
100
www.xilinx.com
1-800-255-7778
5.55
75
(1)
Frequency (MHz)
CC
vs Frequency
150
LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
CoolRunner-II CPLDs are also 1.5V I/O compatible with the
use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C64
7.35
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
1.5V I/O
100
I/O Types
Frequency (MHz)
200
10.87
150
-5, -7.5
Output
V
12.54
175
250
CCIO
3.3
3.3
2.5
1.8
1.5
DS092_01_030102
14.22
200
V
Input
300
3.3
3.3
2.5
1.8
1.5
Advance Product Specification
CCIO
DS092 (v1.2) May 13, 2002
15.91
225
Input
V
N/A
N/A
N/A
N/A
N/A
REF
17.56
Termination
250
Voltage V
Board
N/A
N/A
N/A
N/A
N/A
18.9
270
T
R