DS092 Xilinx Corp., DS092 Datasheet

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DS092

Manufacturer Part Number
DS092
Description
Xc2c64 Coolrunner-ii CPLD
Manufacturer
Xilinx Corp.
Datasheet
DS092 (v1.2) May 13, 2002
Features
Refer to the CoolRunner™-II family data sheet for architec-
ture description.
DS092 (v1.2) May 13, 2002
Advance Product Specification
Optimized for 1.8V systems
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Available in multiple package options
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Advanced system features
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© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
As fast as 4.0 ns pin-to-pin logic delays
As low as 15 A quiescent current
64 macrocells with up to 1,600 logic gates
Fast input registers
Slew rate control on individual outputs
LVCMOS 1.8V through 3.3V
1.5V I/O compatible
LVTTL 3.3V
44-pin PLCC with 33 user I/O
44-pin VQFP with 33 user I/O
56-ball CP BGA with 45 user I/O
100-pin VQFP with 64 user I/O
Fastest in system programming
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IEEE1149.1 JTAG Boundary Scan Test
Optional Schmitt-trigger input (per pin)
Fast Zero Power™ (FZP) 100% CMOS product
term generation
Flexible clocking modes
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Global signal options with macrocell control
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Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
Advanced design security
Open-drain output option for Wired-OR and LED
drive
Optional configurable grounds on unused I/Os
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
PLA architecture
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Hot pluggable
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
1.8V ISP using IEEE 1532 (JTAG) interface
Optional DualEDGE triggered registers
Multiple global clocks with phase selection per
macrocell
Multiple global output enables
Global set/reset
Superior pinout retention
100% product term routability across function
block
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www.xilinx.com
1-800-255-7778
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XC2C64 CoolRunner-II CPLD
Advance Product Specification
Description
The CoolRunner-II 64-macrocell device is designed for both
high performance and low power applications. This lends
power savings to high-end communication equipment and
high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved
This device consists of four Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as "fast input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asyncho-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
The CoolRunner-II 64-macrocell CPLD is I/O compatible
with standard LVTTL and LVCMOS18, LVCMOS25, and
LVCMOS33 (see
patible with the use of Schmitt-trigger inputs.
Table
1). This device is also 1.5V I/O com-
1

Related parts for DS092

DS092 Summary of contents

Page 1

... Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS092 (v1.2) May 13, 2002 Advance Product Specification ...

Page 2

... Frequency (MHz) Figure Frequency CC (1) = 25°C) A Frequency (MHz 100 1.85 3.69 5.55 7.35 10.87 www.xilinx.com 1-800-255-7778 Output Input Input CCIO CCIO REF 3.3 3.3 N/A 3.3 3.3 N/A 2.5 2.5 N/A 1.8 1.8 N/A 1.5 1.5 N/A -5, -7.5 250 300 DS092_01_030102 150 175 200 225 12.54 14.22 15.91 17.56 DS092 (v1.2) May 13, 2002 Advance Product Specification R Board Termination Voltage V T N/A N/A N/A N/A N/A 250 270 18.9 ...

Page 3

... Dynamic current (-5, - Dynamic current (- JTAG input capacitance JTAG C Global clock input capacitance CLK C I/O capacitance IO DS092 (v1.2) May 13, 2002 Advance Product Specification Description (1) (1) Parameter Commercial T = 0°C to +70°C A Industrial T = –40°C to +85°C A (Over Recommended Operating Conditions) Test Conditions ...

Page 4

... MHz MHz MHz www.xilinx.com 1-800-255-7778 Min. Max. Units 3.0 3 0.3V V CCIO –0.3 0.8 V – 0. – 0.2 V – – Min. Max. Units 2.3 2.7 V 1.7 3.9 V –0.3 0.7 V – 0. – 0.2 V – – DS092 (v1.2) May 13, 2002 Advance Product Specification R ...

Page 5

... Low level output voltage OL I Input leakage current IL I I/O High-Z leakage IH C JTAG input capacitance JTAG C Global clock input capacitance CLK C I/O capacitance IO Notes: 1. Hysteresis used on 1.5V inputs. DS092 (v1.2) May 13, 2002 Advance Product Specification Test Conditions I = –8 mA 1.7V OH CCIO I = –0.1 mA 1.7V OH CCIO mA 1.7V OL CCIO I = 0.1 mA ...

Page 6

... OR array. EXT2 DS092 (v1.2) May 13, 2002 Advance Product Specification R Units 6 6.0 ns MHz MHz MHz MHz MHz - 6.8 ns 7.0 ns 7.3 ns 9.2 ns 9 ...

Page 7

... Hysteresis input adder HYS15 T Output adder OUT15 T Output slew rate adder SLEW15 I/O Standard Time Adder Delays 1.8V CMOS T Standard input adder IN18 T Hysteresis input adder HYS18 T Output adder OUT18 T Output slew rate adder SLEW DS092 (v1.2) May 13, 2002 Advance Product Specification -4 (1) Min. Max. - 1.3 - 1.6 - 1.2 - 1.9 - 1.4 - 1.6 - 2.5 - ...

Page 8

... Output slew rate adder SLEW33 Notes: 1. 1.5 ns input pin signal rise/fall. Switching Characteristics 1.8V 6.0 5.8 5.6 4.4 4.2 4 Number of Outputs Switching 8 -4 (1) Min. Max. - 0.5 - 1.5 - 1.5 - 2.0 - 0.7 - 1.0 - 1 DS092_09_121501 www.xilinx.com 1-800-255-7778 -5 -7 Min. Max. Min. Max. - 0.8 - 1.0 - 2.5 - 3.0 - 2.5 - 3.0 - 3.0 - 4.0 - 1.0 - 2.0 - 2.0 - 3.0 - 2.0 - 3.0 - 3.0 - 4.0 DS092 (v1.2) May 13, 2002 Advance Product Specification R Units ...

Page 9

... DS092 (v1.2) May 13, 2002 Advance Product Specification Pin Descriptions (Continued) Function Block CP56 VQ100 ...

Page 10

... DS092 (v1.2) May 13, 2002 Advance Product Specification R Comm. (C) Ind. ( ...

Page 11

... CCIO I TDI 16 TMS 17 TCK (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset Figure 2: PC44 Package K I I/O C I/O B I/O A (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset DS092 (v1.2) May 13, 2002 Advance Product Specification I/O (1) I/O (2) 39 I/O (1) I/O 38 I/O (1) I/O 37 I/O (3) GND 36 I/O I/O 35 I/O I CCIO V I/O ...

Page 12

... Updated AC Electrical Characteristics and added new parameters 12 VQ100 Top View Figure 5: VQ100 Package Revision www.xilinx.com 1-800-255-7778 I/O I I/O 69 GND 68 I GND 61 I I/O 57 Vcc 56 I I CCIO and parameter from DS092 (v1.2) May 13, 2002 Advance Product Specification R ...

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