P10C68- ZARLINK [Zarlink Semiconductor Inc], P10C68- Datasheet - Page 9

• Manufacturer Part Number: P10C68-
• Description: CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

STORE CYCLE 2 : E (BAR) CONTROLLED (See note 13)
NOTES
16. E (bar), G (bar), NE (bar) and W (bar) must make the transition between VIH(max) to VIL(max), or VIL(max) to VIH(min) in a
monotonic fashion.
17. Measured with W (bar) and NE (bar) both returned high, and G (bar) returned low. Note that store cycles are inhibited/aborted
by Vcc <3.3V (STORE inhibit).
18. Once twc has been satisfied by NE (bar), G (bar), W (bar) and E (bar) the store cycle is completed automatically, ignoring all
inputs. Any of NE (bar), G (bar), W (bar) or E (bar) may be used to terminate the store initiation cycle.
Standard
t
ELQX1
t
t
t
t
WLEL
ELNH
GHEL
NLEL
(DATA
OUT)
DQ
(DATA
Symbol
OUT)
DQ
NE
W
G
E
NE
W
G
E
Alternative
t
STORE
t
WC
Store cycle time
NE (bar) set-up to chip enable
Write enable wet-up to chip enable
Chip enable to NE (bar) rise
Output disable set-up to E (bar) fall
t
GHNL
HIGH IMPEDANCE
t
ELWL
t
GHEL
t
WLEL
Parameter
t
NLWL
t
NLEL
HIGH IMPEDANCE
t
t
WLNH
ELNH
Min.
45
P10C68-35
0
0
0
t
ELQX1
t
WLQX
Max.
10
Min.
45
P10C68-45
0
0
0
Max.
10
P10C68/P11C68
Units
ms
ns
ns
ns
ns
Notes
17
18
9