M25P128-VMF6G STMICROELECTRONICS [STMicroelectronics], M25P128-VMF6G Datasheet
M25P128-VMF6G
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M25P128-VMF6G Summary of contents
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... ECOPACK® (RoHS compliant) January 2006 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. With 50MHz SPI Bus Interface VDFPN8 (ME) 8x6mm (MLP8) SO16 (MF) 300 mils width Rev. 1 M25P128 PRELIMINARY DATA 1/41 www.st.com 1 ...
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... Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR 6.4.1 6.4.2 6.4.3 6.4.4 6.5 Write Status Register (WRSR 2/41 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Rev. 1 M25P128 ...
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... M25P128 6.6 Read Data Bytes (READ 6.7 Read Data Bytes at Higher Speed (FAST_READ 6.8 Page Program (PP 6.9 Sector Erase (SE 6.10 Bulk Erase (BE Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Rev ...
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... Table 13. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 14. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 15. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 16. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width . . . . . . . . . . . . . . . . . . . . 38 Table 17. Ordering Information Scheme Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4/41 Rev. 1 M25P128 ...
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... M25P128 List of figures Figure 1. Logic Diagram Figure 2. VDFPN Connections Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Bus Master and Memory Devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. SPI Modes Supported Figure 6. Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 8. Write Enable (WREN) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9. Write Disable (WRDI) Instruction Sequence Figure 10 ...
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... Summary description 1 Summary description The M25P128 is a multilevel 128Mbit (16Mbit x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 64 sectors, each containing 1024 pages. Each page is 256 bytes wide ...
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... See Package mechanical Figure 3. SO Connections Don’t Use 2. See Package mechanical M25P128 AI11314 section for package dimensions, and how to identify pin-1. M25P128 HOLD ...
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... To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register). 8/41 Rev. 1 M25P128 ...
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... M25P128 3 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). ...
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... When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Standby Power mode. The device consumption drops to I 10/41 Table 14: AC Characteristics). ). Rev Section 6.8: Page , M25P128 ). The BE . CC1 ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P128 features the following data protection mechanisms: Power On Reset and an internal timer (t changes while the power supply is outside the operating specification. ...
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... To restart communication with the device necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition. Figure 6. Hold Condition Activation C HOLD 12/41 Figure 6). Hold Condition (standard use) Rev. 1 M25P128 Figure 6). Hold Condition (non-standard use) AI02029D ...
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... M25P128 5 Memory Organization The memory is organized as: 16777216 bytes (8 bits each) 64 sectors (2Mbits, 262144 bytes each) 65536 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable. ...
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... BC0000h B80000h B40000h B00000h AC0000h A80000h A40000h A00000h 9C0000h 980000h 940000h 900000h 8C0000h 880000h 840000h 800000h 7C0000h 780000h 740000h Rev. 1 M25P128 FFFFFFh FBFFFFh F7FFFFh F3FFFFh EFFFFFh EBFFFFh E7FFFFh E3FFFFh DFFFFFh DBFFFFh D7FFFFh D3FFFFh CFFFFFh CBFFFFh C7FFFFh C3FFFFh BFFFFFh BBFFFFh B7FFFFh B3FFFFh ...
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... M25P128 Table 3. Memory Organization (continued) Sector Address Range 700000h 6C0000h 680000h 640000h 600000h 5C0000h 580000h 540000h 500000h 4C0000h 480000h 440000h 400000h 3C0000h 380000h 340000h 300000h 2C0000h 280000h ...
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... Bulk Erase 16/41 Table 4. One-byte Instruction Description Code 0000 0110 0000 0100 1001 1111 0000 0101 0000 0001 0000 0011 0000 1011 0000 0010 1101 1000 1100 0111 Rev. 1 M25P128 Address Dummy Data Bytes Bytes Bytes 06h 04h 9Fh ...
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... M25P128 6.1 Write Enable (WREN) The Write Enable (WREN) instruction The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High ...
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... Figure 10. Read Identification (RDID) Instruction Sequence and Data-Out Sequence High Impedance Q 18/41 Figure 10. Memory Type 20h Instruction Manufacturer Identification MSB Rev. 1 M25P128 Device Identification Memory Capacity 18h Device Identification MSB AI06809b ...
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... M25P128 6.4 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device ...
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... Instructions Figure 11. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence High Impedance Q 20/ Instruction Status Register Out MSB Rev. 1 Status Register Out MSB M25P128 7 AI02031E ...
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... M25P128 6.5 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL) ...
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... Software Protected Mode (SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used. Figure 12. Write Status Register (WRSR) Instruction Sequence 22/ Instruction Register High Impedance MSB Rev. 1 M25P128 Status AI02282D ...
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... M25P128 6.6 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that ...
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... Instruction 24 BIT ADDRESS Dummy Byte DATA OUT MSB Rev DATA OUT MSB M25P128 0 7 MSB AI04006 ...
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... M25P128 6.8 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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... Data Byte 2 Data Byte MSB Rev Data Byte MSB Data Byte 256 MSB M25P128 AI04082B ...
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... M25P128 6.9 Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) ...
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... The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 17. Bulk Erase (BE) Instruction Sequence 28/41 Figure 17 Instruction D Rev initiated. While the AI03752D M25P128 ...
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... M25P128 7 Power-up and power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay Power-down SS Usually a simple pull-up resistor on Chip Select (S) can be used to ensure safe and proper Power-up and Power-down ...
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... FFh). The Status Register contains 00h (all Status Register bits are 0). 30/41 Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed tVSL tPUW Threshold WI Parameter Rev. 1 M25P128 Read Access allowed Device fully accessible time AI04009C Min. Max ...
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... M25P128 9 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability ...
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... Timing Reference Levels 0.8V CC 0.2V CC Parameter Test Condition V OUT V IN =25°C and a frequency of 20 MHz. A Rev. 1 Min. Max. 2.7 3.6 –40 85 Min. Max 0. 0. Input and Output 0.7V CC 0.5V CC 0.3V CC AI07455 Min. Max M25P128 Unit V °C Unit Unit pF pF ...
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... M25P128 Table 13. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Standby Current CC1 I Operating Current (READ) CC3 I Operating Current (PP) CC4 Operating Current I CC5 (WRSR) I Operating Current (SE) CC6 I Operating Current (BE) CC7 V Input Low Voltage IL V Input High Voltage ...
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... C Rev. 1 and Table 11 Min. Typ. Max. D. 0.1 0 100 100 5 15 2 105 250 M25P128 Unit MHz MHz ns ns V/ns V/ ...
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... M25P128 Figure 20. Serial Input Timing S tCHSL C tDVCH D Q Figure 21. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL High Impedance Q tSLCH tCHDX tCLCH MSB IN High Impedance Rev and AC parameters tSHSL tCHSH tSHCH tCHCL LSB IN AI01447C tSHWL AI07439 ...
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... DC and AC parameters Figure 22. Hold Timing HOLD Figure 23. Output Timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D 36/41 tHLCH tCHHL tCHHH tHLQZ tCH tCLQV tQLQH tQHQL Rev. 1 M25P128 tHHCH tHHQX AI02032 tCL tSHQZ LSB OUT AI01449e ...
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... M25P128 11 Package mechanical Figure 24. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. Table 15. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm, ...
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... Min Max 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.10 10.50 7.40 7.60 1.27 – – 10.00 10.65 0.25 0.75 0.40 1.27 0° 8° 0.10 Rev 45˚ ddd inches Typ Min 0.093 0.004 0.013 0.009 0.398 0.291 0.050 – 0.394 0.010 0.016 0° M25P128 Max 0.104 0.012 0.020 0.013 0.413 0.299 – 0.419 0.030 0.050 8° 0.004 ...
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... ST Sales Office. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. M25P128 – Rev. 1 ...
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... Packages are ECOPACK® compliant. Blank option removed under 1 Plating Technology in instruction removed. I Characteristics. Rev. 1 Changes updated. Section 6.3: Read Identification Table 14: AC Characteristics and t Threshold. Modified information and Section 6.8: Page Program Table 17. Read Electronic Signature (RES) parameter updated in Table 13: DC CC1 M25P128 (RDID). value in VSL ...
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... M25P128 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...