A43L2616AG-6 AMICC [AMIC Technology], A43L2616AG-6 Datasheet - Page 12

• Manufacturer Part Number: A43L2616AG-6
• Description: 1M X 16 Bit X 4 Banks Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

Device Operations
Clock (CLK)
The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between V
high all inputs are assumed to be in valid state (low or high)
for the duration of set up and hold time around positive
edge of the clock for proper functionality and ICC
specifications.
Clock Enable (CLK)
The clock enable (CKE) gates the clock onto SDRAM. If
CKE goes low synchronously with clock (set-up and hold
time same as other inputs), the internal clock is suspended
form the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes
low. When both banks are in the idle state and CKE goes
low synchronously with clock, the SDRAM enters the power
down mode form the next clock cycle. The SDRAM
remains in the power down mode ignoring the other inputs
as long as CKE remains low. The power down exit is
synchronous as the internal clock is suspended. When
CKE goes high at least “t
going edge of the clock, then the SDRAM becomes active
from the same clock edge accepting all the input
commands.
Bank Select (BS0, BS1)
This SDRAM is organized as 4 independent banks of
1,048,576 words X 16 bits memory arrays. The BS0, BS1
inputs is latched at the time of assertion of RAS and
to select the bank to be used for the operation. The bank
select BS0, BS1 is latched at bank activate, read, write
mode register set and precharge operations.
Address Input (A0 ~ A11)
The 20 address bits required to decode the 262,144 word
locations are multiplexed into 12 address input pins
(A0~A11). The 12 bit row address is latched along with
bit column address is latched along with
and BS1during read or write command.
NOP and Device Deselect
When RAS ,
performs no operation (NOP). NOP does not initiate any
new operation, but is needed to complete operations which
require more than single clock like bank activate, burst
read, auto refresh, etc. The device deselect is also a NOP
and is entered by asserting CS high. CS high disables
PRELIMINARY
RAS , BS0 and BS1 during bank activate command. The 8
CAS
(November, 2004, Version 0.0)
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and
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. During operation with CKE
are high, the SDRAM
CLOCK
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, BS0
11
the command decoder so that RAS ,
all the address inputs are ignored.
Power-Up
The following sequence is recommended for POWER UP
1. Power must be applied to either CKE and DQM inputs to
2. After VDD reaches the desired voltage, a minimum
3. Both banks must be precharged now.
4. Perform a minimum of 2 Auto refresh cycles to stabilize
5. Perform a MODE REGISTER SET cycle to program the
Mode Register Set (MRS)
The mode register stores the data for controlling the
various operation modes of SDRAM. It programs the CAS
latency, addressing mode, burst length, test mode and
various vendor specific options to make SDRAM useful for
variety of different applications. The default value of the
mode register is not defined, therefore the mode register
must be written after power up to operate the SDRAM. The
mode register is written by asserting low on CS , RAS ,
CKE already high prior to writing the mode register). The
state of address pins A0~A11, BS0 and BS1 in the same
cycle as CS , RAS ,
written in the mode register. One clock cycle is required to
complete the write in the mode register. The mode register
contents can be changed using the same command and
clock cycle requirements during operation as long as both
banks are in the idle state. The mode register is divided
into various fields depending on functionality. The burst
length field uses A0~A2, burst type uses A3, addressing
mode uses A4~A6, A7~A8, A11, BS0 and BS1 are used for
vendor specific options or test mode. And the write burst
length is programmed using A9. A7~A8, A11, BS0 and BS1
must be set to low for normal SDRAM operation.
Refer to table for specific codes for various burst length,
addressing modes and CAS latencies.
CAS
pull them high and other pins are NOP condition at the
inputs before or along with VDD (and VDDQ) supply.
The clock signal must also be asserted at the same time.
pause of 200 microseconds is required with inputs in
NOP condition.
the internal circuitry.
CAS latency, burst length and burst type as the default
value of mode register is undefined.
At the end of one clock cycle from the mode register set
cycle, the device is ready for operation.
When the above sequence is used for Power-up, all the
out-puts will be in high impedance state. The high
impedance of outputs is not guaranteed in any other
power-up sequence.
cf.) Sequence of 4 & 5 may be changed.
,
WE
(The SDRAM should be in active mode with
CAS
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going low is the data
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