lc8901 Sanyo Semiconductor Corporation, lc8901 Datasheet

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lc8901

Manufacturer Part Number
lc8901
Description
Digital Audio Interface Receiver
Manufacturer
Sanyo Semiconductor Corporation
Datasheet
Overview
The LC8901 and LC8901Q are LSIs for use in IEC958,
EIAJ CP-1201 format data transmission between digital
audio equipment. These LSIs are used on the receiving
side, and handle synchronization with the input signal and
demodulation of that signal to a normal format signal.
Features
• On-chip PLL circuit synchronizes with the transmitted
• Provides 20-bit LSB first and 16-bit MSB first audio
• Microprocessor interface for mode settings and code
• System clock can be selected to be either 384fs or 512fs.
• Provides both a digital source mode and an analog
• Fabricated in a Si-gate CMOS process.
• 5 V single-voltage power supply
Ordering number : EN4079B
IEC958, EIAJ CP-1201 format signal.
data output functions.
output
source mode.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Package Dimensions
unit: mm
3025B-DIP42S
unit: mm
3148-QIP44M
Digital Audio Interface Receiver
D3095HA (OT)/52593JN/7202JN No. 4079-1/15
[LC8901Q]
[LC8901]
LC8901, 8901Q
SANYO: QIP44M
SANYO: DIP42S
CMOS LSI

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lc8901 Summary of contents

Page 1

... Ordering number : EN4079B Overview The LC8901 and LC8901Q are LSIs for use in IEC958, EIAJ CP-1201 format data transmission between digital audio equipment. These LSIs are used on the receiving side, and handle synchronization with the input signal and demodulation of that signal to a normal format signal. ...

Page 2

... Usage overview diagram Assumes the use of both digital and analog source modes. Digital source mode Analog source mode Pin Assignment LC8901 (DIP42S) LC8901, 8901Q LC8901Q (QIP44M) No. 4079-2/15 ...

Page 3

... Block Diagram LC8901, 8901Q No. 4079-3/15 ...

Page 4

... Used to start system operation after power on — Digital system power supply DD Note: The DIP42S package version has one fewer each of the digital system power supply and digital system ground pins than the QIP44M package version. LC8901, 8901Q Pin function and circuit operation No. 4079-4/15 ...

Page 5

... Microprocessor interface clock input 38 XMODE I Used to start system operation after power on — Digital system power supply DD 40 DIN1 I 41 DIN2 I Data input pins with built-in amplifiers 42 DIN3 I 43 DIN4 I 44 DGND — Digital system ground LC8901, 8901Q Pin function and circuit operation No. 4079-5/15 ...

Page 6

... WBO Output setup time t DSO Output data hold time t DHO Output delay for high tbdH Output delay for low tbdL Note: Load capacitance: Each pin has a load capacitance of 30 pF. LC8901, 8901Q Symbol Conditions max DD V max IN max OUT Topr Tstg Conditions = 4 ...

Page 7

... CL, CE delay time TD1 CL delay time TD2 Data delay time TD3 With load CL and data delay time TD4 With load CL delay time TD5 CL and CE delay time TD6 LC8901, 8901Q = 4 Conditions min 100 100 50 50 1.0 50 100 1.0 typ max ...

Page 8

... Waveforms for the Microprocessor Interface Block Input mode Output mode Clock Modes The LC8901 and LC8901Q support 4 clock modes selected by the XSYS and CLK pins. XSYS pin CLK pin L L The system clock is 384fs synchronized to the input data, which is then demodulated. ...

Page 9

... Bits the format figure are the address. There are two dedicated addresses allocated, one for data input and one for data output. Use the input address for data input and the output address for data output. Address Codes Mode Data input Data output LC8901, 8901Q No. 4079-9/15 ...

Page 10

... There are two audio data output modes, one with a 16-bit MSB first format and one with a 20-bit LSB first format. The I14 code determines the setting. I14 L Audio data output mode 16-bit MSB first format LC8901, 8901Q plus 0.3 V. Pins DIN5 and DIN6 do not have built-in amplifiers and are ...

Page 11

... These pins indicate a state identical to a PLL lock error in any of the following cases: The STOP pin is high, the XMODE pin is low, or the system is in analog source mode. LC8901, 8901Q Meaning 48 kHz ...

Page 12

... The microprocessor interface pins must not be accessed until the XMODE pin has gone high and the system has started to operate. 3. The data output pins must not be accessed until the ERROR pin has gone low after the XMODE pin has gone high. LC8901, 8901Q No. 4079-12/15 ...

Page 13

... Data Output Timing The figure below shows the data output timing. 1. Data is output in synchronization with the falling edge of the BCLK signal. 2. Data, BCLK, and LRCK are output in synchronization with the rising edge of the 256fs clock. Timing Chart LC8901, 8901Q No. 4079-13/15 ...

Page 14

... Note: * The constants listed above are for applications that connect to the input pins using coaxial cable. If connection is through an optical receiver module, remove the C1 capacitors and use 56 k resistors for R1. Note that DIN5 and DIN6 are only for use with optical receiver modules. LC8901, 8901Q No. 4079-14/15 ...

Page 15

... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. LC8901, 8901Q No. 4079-15/15 ...

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