lc8905v Sanyo Semiconductor Corporation, lc8905v Datasheet
lc8905v
Related parts for lc8905v
lc8905v Summary of contents
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... Ordering number : EN*5237 Preliminary Overview The LC8905V is for use in IEC 958 and EIAJ CP-1201 format data transmission between digital audio equipment. This LSI is used on the receiving side, and handles synchronization with the input signal and demodulation of that signal to a normal format signal. ...
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... Microprocessor interface subcode Q and ID synchronization output 19 CKOUT O VCO clock output (free running, 384fs, or 512fs) 20 FS128 O 128fs clock output 21 BCK O Bit clock output 22 LRCK O L/R clock output (left channel = high, right channel = low) 23 DATAOUT O Audio data output 24 ERROR O PLL lock error mute output LC8905V Description No. 5237-2/16 ...
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... Block Diagram LC8905V No. 5237-3/16 ...
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... Parameter Symbol Input pulse width t WBI Output pulse width kHz WBO Output data setup time t DSO Output data hold time t DHO Output delay t BD LC8905V Symbol Conditions max DD V max I O Topr Tstg Conditions = 4 Conditions = –1 µ µ ...
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... LC8905V No. 5237-5/16 ...
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... CE delay time delay time delay time pulse width 44.1 kHz W Data delay time Data delay time Input mode Output mode LC8905V Conditions min 100 100 50 50 1.0 50 typ max Unit µs ns 100 ns 136 µs 75 ...
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... Data hold time delay time pulse width 44.1 kHz W Data delay time Data delay time Input mode Output mode LC8905V Conditions min 100 100 50 50 100 typ max Unit µs 136 µ ...
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... DATAOUT pins. The CKOUT clock output is set by the CKSEL pin as listed in the table below. CKSEL CKOUT L 384fs clock output H 512fs clock output The microprocessor interface format is also set by CKSEL as listed in the table below. CKSEL Microprocessor interface L Figure 2 H Figure 3 LC8905V No. 5237-8/16 ...
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... LC8905V Figure 1 Data Output Timing No. 5237-9/16 ...
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... LC8905V Figure 2 Microprocessor Interface Timing 1 No. 5237-10/16 ...
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... LC8905V Figure 3 Microprocessor Interface Timing 2 No. 5237-11/16 ...
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... DI5 and DI6: Set the audio data output format. DI5 L DI6 L 16-bit right- 20-bit right- DATAOUT justified justified MSB first LSB first All bits are set low immediately after XMODE is switched from low to high. DI0 and DI7 are not used. LC8905V ...
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... Flags + 80 data bits all H Detected ID Start ID • Output pins The output scheme used for SRDT/DO differs depending on the microprocessor interface format selected by CKSEL. CKSEL Format L Figure 2 H Figure 3 LC8905V ) or a shortening the start all L Shortening ID SRDT/DO Open-drain output ...
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... Normal system operation is started by setting XMODE high after the power supply has risen above at least 4 XMODE is set low, the VCO free-running oscillator clock is output from CKOUT. Setting XMODE low once again after power on resets the system. LC8905V DATAOUT C bit Sub Q ...
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... Sample Application Circuit LC8905V No. 5237-15/16 ...
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... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. LC8905V No. 5237-16/16 ...