w3e16m72s-xbx White Electronic Designs Corporation, w3e16m72s-xbx Datasheet - Page 14

• Manufacturer Part Number: w3e16m72s-xbx
• Description: 16mx72 Sdram
• Manufacturer: White Electronic Designs Corporation

29. The Input capacitance per pin group will not differ by more than this maximum
30. CLK and CLK# input slew rate must be ≥ 1V/ns (≥2V/ns differentially).
31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the
32. V
33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary
34. t
35. READs and WRITEs with auto precharge are not allowed to be issued until t
36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or
37. Normal Output Drive Curves:
38. Reduced Output Drive Curves:
February 2005
Rev. 7
FIGURE C – PULL-DOWN CHARACTERISTICS
amount for any given device.
DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be
added to t
4V/ns, functionality is uncertain.
by the same amount.
CLK and CLK# inputs, collectively during bank active.
can be satisfi ed prior to the internal precharge command being issued.
2.9 volts, whichever is less. Any negative glitch must be less than 1/3 of the clock
cycle and not exceed either -300mV or 2.2 volts, whichever is more positive.
a) The full variation in driver pull-down current from minimum to maximum process,
b) The variation in driver pull-down current within nominal limits of voltage and
c) The full variation in driver pull-up current from minimum to maximum process,
d) The variation in driver pull-up current within nominal limits of voltage and
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down
f) The full variation in the ratio of the nominal pull-up to pull-down current should be
a) The full variation in driver pull-down current from minimum to maximum process,
b) The variation in driver pull-down current within nominal limits of voltage and
c) The full variation in driver pull-up current from minimum to maximum process,
HP
CC
unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt.
temperature and voltage will lie within the outer bounding lines of the V-I curve of
Figure B.
temperature and voltage will lie within the outer bounding lines of the V-I curve of
Figure D.
min is the lesser of t
temperature and voltage will lie within the outer bounding lines of the V-I curve of
Figure A.
temperature is expected, but not guaranteed, to lie within the inner bounding lines
of the V-I curve of Figure A.
temperature is expected, but not guaranteed, to lie within the inner bounding lines
of the V-I curve of Figure B.
current should be between .71 and 1.4, for device drain-to-source voltages from
0.1V to 1.0 Volt, and at the same voltage and temperature.
temperature and voltage will lie within the outer bounding lines of the V-I curve of
Figure C.
temperature is expected, but not guaranteed, to lie within the inner bounding lines
of the V-I curve of Figure C.
must not vary more than 4% if CKE is not active while any bank is active.
80
70
60
50
40
30
20
10
0
0.0
DS
and t
DH
for each 100mV/ns reduction in slew rate. If slew rate exceeds
0.5
White Electronic Designs
CL
minimum and t
1.0
V
CH
OUT
minimum actually applied to the device
(V)
1.5
2.0
Nominal high
Nominal low
Maximum
Minimum
RAS
2.5
(MIN)
14
39. The voltage levels used are derived from a minimum V
40. V
41. V
42. This maximum value is derived from the referenced test load. In practice, the values
43. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier.
44. During initialization, V
45. The current part operates below the slowest JEDEC operating frequency of 83 MHz.
46. Reserved for future use.
47. Reserved for future use.
48. Random addressing changing 50% of data changing at every transfer.
49. Random addressing changing 100% of data changing at every transfer.
50. CKE must be active (high) during the entire time a refresh command is executed.
51. I
52. Whenever the operating frequency is altered, not including jitter, the DLL is required
53. V
d) The variation in driver pull-up current within nominal limits of voltage and
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down
f) The full variation in the ratio of the nominal pull-up to pull-down current should be
test load. In practice, the voltage levels obtained from a properly terminated bus will
provide signifi cantly different voltage values.
can not be greater than 1/3 of the cycle rate.
obtained in a typical terminated design may refl ect up to 310ps less for t
and the last DVW. t
t
Alternatively, V
volts, provided a minimum of 42 ohms of series resistance is used between the V
supply and the input pin.
As such, future die may not refl ect this option.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until t
I
remain stable. Although I
to be reset. This is followed by 200 clock cycles before any READ command.
equal to zero to avoid device latch-up. V
less than V
V
the V
within the specifi ed range.
FIGURE D – PULL-UP CHARACTERISTICS
LZ
CC2N
CC2Q
IH
CC
TT
CC
(MIN) will prevail over t
unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 V.
temperature is expected, but not guaranteed, to lie within the inner bounding lines
of the V-I curve of Figure D.
current should be between .71 and 1.4, for device drain-to-source voltages from
0.1V to 1.0 V, and at the same voltage and temperature.
overshoot: V
/V
is not applied directly to the device; however, t
and V
TT
-10
-20
-30
-40
-50
-60
-70
-80
specifi es the DQ, DQS, and DM to be driven to a valid high or low logic level.
is similar to I
CCQ
0
supply and the input pin. Once initialized, V
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0.0
are 0V, provided a minimum of 42 Ω of series resistance is used between
CCQ
CC
+ 0.3V. Alternatively V
must track each other.
TT
IH
may be 1.35V maximum during power up, even if V
(MAX) = V
CC2F
HZ
(MAX) will prevail over t
CCQ
0.5
except I
CC2F
, V
DQSCK
TT
CCQ
, I
, and V
CC2Q
CC2N
(MIN) + t
+1.5V for a pulse width ≤ 3ns and the pulse width
, and I
specifi es the address and control inputs to
1.0
TT
W3E16M72S-XBX
V
REF
CCQ -
RFC
may be 1.35V max during power-up even if
RPRE
CCQ
must be equal to or less than V
CC2Q
has been satisfi ed.
V
OUT
, V
(MAX) condition.
DQSCK
are similar, I
TT
(V)
and V
1.5
VTD
(MAX) + t
REF
should be greater than or
CC
REF
must always be powered
level and the referenced
CC2F
must be equal to or
RPST
2.0
is “worst case.”
Nominal high
(MAX) condition.
Nominal low
Maximum
Minimum
CC
HZ
/V
CC
CCQ
(MAX)
+ 0.3V.
2.5
are 0
TT