cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 38
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cx28250
Manufacturer Part Number
cx28250
Description
Cx28250 Atm Physical Interface Phy Devices
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28250.pdf
(213 pages)
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2.0 Functional Description
Figure 2-2. CX28250 Receiver Block Diagram
2-2
External Clock Recovery
PECL
Data
NRZ
Recovery
Clock
Rx Clock
Figure 2-2
clock from the incoming data stream and converts the serial data stream to
parallel and passes it to the framer block, which extracts the overhead bytes. HEC
alignment is performed to recover the Start of Cell boundary. The cells are then
sent over the UTOPIA bus to the ATM layer device.
MUX
Serial to
Parallel
Mindspeed Technologies
shows the CX28250 receive signal path. The CX28250 recovers the
Framer
Octets
Align.
HEC
™
ATM Physical Interface (PHY) Devices
Processor
Overhead
Receiver
ATM
Cell
Overhead Output
28250-DSH-002-C
UTOPIA
FIFO
CX28250
500035_007
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