89ttm552 Integrated Device Technology, 89ttm552 Datasheet - Page 8

• Manufacturer Part Number: 89ttm552
• Description: Standalone 10g Simplex Traffic Manager
• Manufacturer: Integrated Device Technology

IDT 89TTM552
MC_DOUT[17:0]
MC_BW_N[1:0]
MC_VREF[1:0]
SAR_CLK_CP (C),
SAR_CLK_CN (C#)
SAR_CLK_KP (K),
SAR_CLK_KN (K#)
SAR_ADDR[21:0]
SAR_RD_N
SAR_WR_N
SAR_DIN[8:0]
SAR_DOUT[8:0]
SAR_VREF
DRAM_CLKP[2:0]
DRAM_CLKN[2:0]
DRAM0_ADDR[12:0]
DRAM0_BNK[1:0]
DRAM0_CAS_N
Signal Name
Signal Name
Signal Name
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
I/O Type
I/O Type
I/O Type
0.75V
0.75V
Table 5 Multicast / Parent-Child QDR SRAM (Part 2 of 2)
Table 7 PIC Buffer (DDR SDRAM) (Part 1 of 2)
Table 6 In-Line SAR (ILS) QDR SRAM
1
Dir.
Dir.
Dir.
—
—
O
O
O
O
O
O
O
O
O
O
O
O
I
I
8 of 37
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
Freq.
Freq.
Freq.
—
—
MC QDR SRAM data outputs: Output data is synchronized to
the K and K# during write operations
MC QDR SRAM byte write enable: This is used with
MC_WR_N when writing to the QDR SRAM. By using these
byte write enable signals, MC logic can write to half of a QDR
RAM entry when programming the logical multicast branch
table.
MC_BW_N[0] controls MC_DOUT[8:0]. MC_BW_N[1] controls
MC_DOUT[17:9].
HSTL reference. Nominally V
ILS QDR SRAM input clock: This clock pair registers data
inputs on the rising edge of C and C#. All synchronous inputs
must meet setup and hold times around the clock rising
edges.
ILS QDR SRAM output clock: This clock pair times the
address and control outputs to the rising edge of K, and times
the data outputs on the rising edge of K and K#.
ILS QDR SRAM address outputs:
ILS QDR SRAM synchronous read output (active low): When
asserted, a read cycle is initiated to the external QDR SRAM
devices.
ILS QDR SRAM synchronous write output (active low): WHen
asserted, a write cycle is initiated to the external QDR SRAM
devices.
ILS QDR SRAM data inputs: Input data must meet setup and
hold times around the rising edges of C and C# during read
operations
ILS QDR SRAM data outputs: Output data is synchronized to
the K and K# during write operations
HSTL reference. Nominally V
DRAM clock, group 0 & group 1
Important: See the footnote.
DRAM clock (“clock bar”)
Group 0 SDRAM address
Group 0 SDRAM bank address
Group 0 column address strobe (active low)
Remarks
Remarks
Remarks
DDQ
DDQ
/ 2, so connect to 0.75 V
/ 2, so connect to 0.75 V
April 7, 2005