89ttm552 Integrated Device Technology, 89ttm552 Datasheet - Page 17

• Manufacturer Part Number: 89ttm552
• Description: Standalone 10g Simplex Traffic Manager
• Manufacturer: Integrated Device Technology

AC Test Conditions
AC Test Conditions
AC Test Conditions
AC Test Conditions
IDT 89TTM552
1.
Input Rise/Fall Time
Output timing measurement reference level (V
Output load
Clock-data alignment is selectable in 1/4 cycle steps; skew is relative to this alignment
Symbol
Symbol
t
t
T
T
D
t
SSCLK
HSCLK
T
T
SKEW
KQHZ
KQLZ
KQV
KQX
T
T
COC
f
S
H
S
Status channel clock frequency
Status clock duty percentage
Status clock to output data skew
Status channel input setup time
Status channel input hold time
Zbus clock high to output valid
Zbus clock high to output invalid
Zbus clock high to output low-Z
Zbus clock high to output high-Z
Input setup time from system clock
Input hold time from system clock
For output timing
Parameter
Z0 = 50
REF
Parameter
) for 3.3V interfaces
Table 22 SPI-4 LVTTL AC Parameters
20 pF
1
Table 23 Zbus Interface Timing
Table 24 AC Test Conditions
Figure 3 AC Test Load
17 of 37
Min
50
75
40
V
2
0
REF
Typical
—
—
—
—
—
For enable/disable spec
Max
125
500
60
—
—
1 V / ns (20% / 80%)
(VDDQ/2) V
As shown in Figure 3
Min
2.5
1.0
1.0
3.0
—
0
Units
MHz
ps
ns
ns
%
Typical
5 pF
—
—
—
—
—
—
VDD
Conditions
Max
8.3
6.0
6.0
75
75
—
—
—
Units
April 7, 2005
ns
ns
ns
ns
ns
ns